CY7C1318V18 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1318V18 Datasheet PDF : 24 Pages
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PRELIMINARY
CY7C1316V18
CY7C1318V18
CY7C1320V18
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±10% is between 175Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles to adjust for drifts in supply voltage and temperature.
Application Example[2]
SRAM #1
Memory
Controller
DQ
18
72
DQ
20
LD
Add.
R/W
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the DDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
of the DDR-II. In the single clock mode, CQ is generated with
respect to K and CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
SRAM #4
DQ
18
20
VTERM = VREF
R = 50Ω
CLK/CLK (input)
CLK/CLK (output)
2
2
R = 50Ω
VT = VREF
Truth Table[3, 4,5, 6, 7, 8]
Operation
K
LD R/W
DQ
DQ
Write Cycle:
L-H
L L D(A1)at K(t + 1) ↑ D(A2) at K(t + 1) ↑
Load address; input write data on consecutive K and K rising
edges.
Read Cycle:
L-H
Load address; wait one cycle; read data on consecutive C and
C rising edges.
L H Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑
NOP: No Operation
L-H H X High-Z
High-Z
Standby: Clock Stopped
Stopped X X Previous State Previous State
Notes:
2. The above application shows 4 of CY7C1318V18 being used. This holds true for CY7C1316V18 and CY7C1320V18 as well.
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
4. Device will power-up deselected and the outputs in a three-state condition.
5. On CY7C1318V18 and CY7C1320V18, “A1” represents address location latched by the devices when transaction was initiated and A2 represents the addresses
sequence in the burst. On CY7C1316V18, “A1” represents A + ‘0’ and A2 represents A + ‘1.’
6. “t” represents the cycle at which a read/write operation is started. t+1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Document #: 38-05177 Rev. *A
Page 7 of 24
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