CY7C1318V18 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1318V18

18-Mb DDR-II SRAM Two-word Burst Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1316V18

CY7C1318V18

CY7C1320V18

18-Mb DDR-II SRAM Two-word

Burst Architecture

Features

Functional Description

• 18-Mb density (2M x 8, 1M x 18, 512K x 36)

— Supports concurrent transactions

• 250-MHz clock for high vandwidth

• Two-word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces (data transferred at

500 MHz) @ 250 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mismatches

• Echo clocks (CQ and CQ) simplify data capture in high

speed systems

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–VDD)

• 13x15 mm 1.0-mm pitch fBGA package, 165 ball (11x15

matrix)

• JTAG interface

• On-chip Delay Lock Loop (DLL)

Configurations

CY7C1316V18 – 2M x 8

CY7C1318V18 – 1M x 18

CY7C1320V18 – 512K x 36

The CY7C1316V18/CY7C1318V18/CY7C1320V18 are 1.8V

Synchronous Pipelined SRAM equipped with DDR-II (Double

Data Rate) architecture. The DDR-II consists of an SRAM core

with advanced synchronous peripheral circuitry and a 1-bit

burst counter. Addresses for Read and Write are latched on

alternate rising edges of the input (K) clock.Write data is regis-

tered on the rising edges of both K and K. Read data is driven

on the rising edges of C and C if provided, or on the rising edge

of K and K if C/C are not provided. Each address location is

associated with two 8-bit words in the case of CY7C1316V18

that burst sequentially into or out of the device. The burst

counter always starts with a “0” internally in the case of

CY7C1316V18. On CY7C1318V18 and CY7C1320V18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words in the case of

CY7C1318V18 and two 36-bit words in the case of

CY7C1320V18 sequentially into or out of the device.

Asynchronous inputs include impedance match (ZQ).

Synchronous data outputs (Q, sharing the same physical pins

as the data inputs D) are tightly matched to the two output echo

clocks CQ/CQ, eliminating the need for separately capturing

data from each individual DDR SRAM in the system design.

Output data clocks (C/C) enable maximum system clocking

and data synchronization flexibility.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Logic Block Diagram (CY7C1316V18)

Burst

Logic

A(19:0)

20

LD

K

K

Address

Register

CLK

Gen.

VREF

R/W

BWS[1:0]

Control

Logic

Write

Reg

Write

Reg

Read Data Reg.

16 8

8

Output

Logic

Control

R/W

C

C

Reg.

Reg.

8

Reg.

8

8

CQ

CQ

DQ[7:0]

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-05177 Rev. *A

Revised July 31, 2002

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