CY7C1316V18 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1316V18

18-Mb DDR-II SRAM Two-word Burst Architecture

Cypress Semiconductor 

TAP Controller State Diagram[21]

1

TEST-LOGIC

RESET

0

0

TEST-LOGIC/ 1

IDLE

PRELIMINARY

SELECT

1

DR-SCAN

0

1

CAPTURE-DR

0

SHIFT-DR

0

1

1

EXIT1-DR

0

PAUSE-DR

0

1

0

EXIT2-DR

1

UPDATE-DR

1

0

Note:

21. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

CY7C1316V18

CY7C1318V18

CY7C1320V18

1

SELECT

IR-SCAN

0

1

CAPTURE-IR

0

SHIFT-IR

0

1

EXIT1-IR

1

0

PAUSE-IR

0

1

0

EXIT2-IR

1

UPDATE-IR

1

0

Document #: 38-05177 Rev. *A

Page 18 of 24

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