CY7C1316V18 Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1316V18

18-Mb DDR-II SRAM Two-word Burst Architecture

Cypress Semiconductor 

PRELIMINARY

Switching Waveforms

Write/Deselect Sequence[19, 20]

Write

K

tKH

Write

Deselect

tKL

K

tSA

A

A

tSC

R/W

tSC

tHC

tHA

tKH

B

tHC

LD

tSC

BWSx

Write

tCYC

tKL

C

CY7C1316V18

CY7C1318V18

CY7C1320V18

Deselect

Deselect

tHC

Data In

D(A)

D(A+1) D(B)

D(B+1)

tSD tHD

= DON’T CARE

Notes:

19. C and C reference to Data Outputs and do not affect Write operations.

20. BWSx LOW = Valid, Byte writes allowed, see Byte write table for details.

= UNDEFINED

D(C)

D(C+1)

Document #: 38-05177 Rev. *A

Page 14 of 24

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