PBL40215 Просмотр технического описания (PDF) - Ericsson
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PBL40215 Datasheet PDF : 22 Pages
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PBL 402 15
The 3-Wire Control Bus Interface.
The 3-wire serial bus interface controls the various IC parameters and consists of 3 lines, strobe, data and clock ( ST, D, CK ).
Alternatively, selected power control modes may be controlled by 3 hard-wire control lines ( EN, RXEN, TXEN ).
The 3-wire bus is active when either EN or ST, or both are active. The strobe signal is used to enable the clock and latch the
data frame. Each frame consists of 24 bits, built from a word field and a data field. The word address is the last bit to be sent
( LSB ), with the data field being the proceeding 23 bits. Data on D is shifted into the frame register by clock CK.
The 3-wire interface allows setting of word A and word B. These control the IC configuration.
Frame definition:
MSB
First in
Frame:
Description
tag:
Data
LSB
Last in
Word
Address
Digital Interface:
Pin
Spec.
ST
Digital input
CK
Digital input
D
Digital input
EN
Digital input
RXEN Digital input
TXEN Digital input
Description
The control section is powered up when ST is low. Data is latched on the rising edge.
ST has an internal 160kΩ pull up resistor to VCC PLL.
3-wire interface clock. May be running continuously, but to minimise the risk of VCO spurious it is
recommended that the clock only runs when required.
3-wire interface data. Data latched by rising edge of CK.
IC enable control. Active low. The control section is powered when EN is active.
EN has an internal 160 kΩ pull up resistor to VCC PLL.
Receiver enable. Active low.
Transmitter enable. Active low.
Digital Interface:
Parameter
Serial clock frequency
Delay strobe to first rising clock
Data setup time: D to CK
Data hold time
Clock pulse widh high
Strobe hold time high
Condition
Symbol
f
CK
tSCK
tDS
tDH
tCKW
tSW
Min.
288
18
18
18
144
Typ.
Max.
13.9
Unit
MHz
ns
ns
ns
ns
ns
9
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