PBL40215 Просмотр технического описания (PDF) - Ericsson
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PBL40215 Datasheet PDF : 22 Pages
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PBL 402 15
Hard Wire Control Lines.
The 3 hardwire control lines EN, RXEN and TXEN allow control of the IC by a controller with limited interface access or capabili-
ties. Typically, controllers with only one access per slot or no access between slots.
For correct operation the 3 hard wire lines require appropriate programming of the CE and CL flags.
The hardwire lines directly force the state of the appropriate word B flags as detailed below.
Hard wire line
EN
RXEN
TXEN
Description
Powers the serial bus interface.
Upon the rising edge of ST and provided CL is set to 1, the effect is as SYN_EN.
Provided EN is active and CL is set to 1, the effect is as IF_EN and RX_EN.
Provided EN is active and CL is set to 1, the effect is as TX_EN.
LO and Modulation Section.
Modulator ×2
IF
÷2
PLL
ƒ-φ
÷R
The LO section consists of a TX VCO with a frequency doubler, a RX VCO and a charge pump PLL.
The VCO´s are fully integrated and are phase/frequency locked to an external reference frequency applied to the REF pin. The
frequency is programmed by the 3-wire interface. Lock detect is available on the LD pin. When neither TX_EN or RX_EN are active,
lock detect is also available at the DRX output.
The RX VCO runs at twice the frequency. The frequency of the RX VCO is divided by 2 for the PLL. The TX VCO runs at half the
TX frequency to improve pulling immunity to TX harmonics. A frequency doubler generates the TX LO for the PLL.
The TX VCO is modulated by an external signal applied to the DTX pin. The DTX input is permanently connected to the TXVCO.
An active MOD_EN signal disables the PLL charge pump output which allows modulation to be applied. A hardware modulation
enable signal may be applied to either the MOD pin or SHOLD pin depending upon setting of the MOD_SW flag.
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