MT9T001 Просмотр технического описания (PDF) - Micron Technology
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MT9T001 Datasheet PDF : 37 Pages
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PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Output Data Timing
The data output of the MT9T001 is synchronized
with the PIXCLK output. When LINE_VALID is HIGH,
one 10-bit pixel datum is output every PIXCLK period.
The PIXCLK can be used as a clock to latch the data.
DOUT data is valid on the falling edge of PIXCLK in
default mode. The PIXCLK is HIGH while master clock
is HIGH and then LOW while master clock is LOW. It is
continuously enabled, even during the blanking
period. The parameters in P, A, and Q shown in
Figure 8 are defined in Table 3.
Figure 7: Timing Example of Pixel Data
LINE_VALID
PIXCLK
Blanking
Valid Image Data
....
....
....
Blanking
DOUT9-DOUT0
(9P:00)
(9P:10)
(9P:20)
(9P:30) (9P:40) . . . .
P(9n:-01)
(9P:n0)
Figure 8: Row Timing and FRAME_VALID/LINE_VALID Signals
FRAME_VALID
LINE_VALID
Number of master clocks P1+P2 A
Q
...
...
...
A
Q
A
P3
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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