MN6732741 Просмотр технического описания (PDF) - Panasonic Corporation
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MN6732741
Panasonic Corporation
MN6732741 Datasheet PDF : 15 Pages
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MN6732741
I Function Descriptions (by circuit block) (continued)
14. SSG
This block generates both low-speed pulse signals used by the CCD and various kinds of pulse signals used for
signal processing. (However, note that VBSGEN locking is not supported.)
15. I2C-bus
When power is first applied, the contents of an external EEPROM are read out and used to set the IC internal
registers.
Since this circuit does not support multi-master operation, no external devices will have become bus master
when power is first applied. This I2C-bus also can be used by external devices to read or write the IC internal registers.
(Note that certain limitations apply.)
I Pin Arrangement
COIN
97
OBCTL
98
EXTAGC
99
IRIS
100
ALCELC
101
ATWLOCK
102
APGAIN
103
BLCSW
104
DIN8
105
DIN7
106
DIN6
107
DIN5
108
DIN4
109
VDD4
110
VSS4
111
DIN3
112
DIN2
113
DIN1
114
DIN0
115
DS2
116
DS1
117
TESTDC2
118
TESTSW5
119
R
120
N.C.
121
TGVDD
122
TGVSS
123
N.C.
124
H2
125
N.C.
126
H1
127
N.C.
128
64
VIN
63
VREFL
62
VREFML
61
ADVDD
60
ADVSS
59
VREFM
58
VREFHM
57
VREFH
56
VREF23
55
IREF23
54
COMP23
53
BSIG
52
DAVSS1
51
DAVDD1
50
RSIG
49
VREF1
48
IREF1
47
COMP1
46
GSIG
45
DAVSS2
44
DAVDD2
43
VCXO
42
LPFI
41
FVR
40
MINTEST
39
SCANT
38
HREFCBLK
37
VCSYNCVD
36
YUVOE
35
NTPL
34
PCO
33
EXTMOD
(TOP VIEW)
4
SDB00060AEM
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