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MAX6746

µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay

Maxim Integrated 

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

ELECTRICAL CHARACTERISTICS (continued)

(VCC = +1.2V to +5.5V, TA = TMIN to TMAX, unless otherwise specified. Typical values are at VCC = +5V and TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Fast Watchdog Timeout Period,

SET Ratio = 64,

(MAX6752/MAX6753)

tWD1

CSWT = 1500pF

CSWT = 100pF

11.38 15.18 18.98

ms

1.01

Fast Watchdog Minimum Period

(MAX6752/MAX6753)

SWT Ramp Current

SWT Ramp Threshold

RESET Output Voltage LOW

Open-Drain, Push-Pull

(Asserted)

RESET Output Voltage HIGH,

Push-Pull (Not Asserted)

RESET Output Leakage Current,

Open Drain

IRAMP

VRAMP

VOL

VOH

ILKG

VSWT = 0 to 1.23V, VCC = 1.6V to 5V

VCC = 1.6V to 5V (VRAMP rising)

VCC ≥ 1.0V, ISINK = 50µA

VCC ≥ 2.7V, ISINK = 1.2mA

VCC ≥ 4.5V, ISINK = 3.2mA

VCC ≥ 1.8V, ISOURCE = 200µA

VCC ≥ 2.25V, ISOURCE = 500µA

VCC ≥ 4.5V, ISOURCE = 800µA

VCC > VTH, reset not asserted,

V RESET = 5.5V

DIGITAL INPUTS (MR, SET0, SET1, WDI, WDS)

Input Logic Levels

MR Minimum Pulse Width

MR Glitch Rejection

MR to RESET Delay

MR Pullup Resistance

WDI Minimum Pulse Width

VIL

VIH

VCC ≥ 4.0V

VIL

VCC < 4.0V

VIH

Pullup to VCC

RESET IN

RESET IN Threshold

RESET IN Leakage Current

RESET IN to RESET Delay

VRESET IN

IRESET IN

TA = -40°C to +125°C

RESET IN falling at 1mV/µs

2000

ns

200 250 300

nA

1.173 1.235 1.297

V

0.3

0.3

V

0.4

0.8 x VCC

0.8 x VCC

V

0.8 x VCC

1.0

µA

0.8

2.4

V

0.3 x VCC

0.7 x VCC

1

µs

100

ns

200

ns

12

20

28

kΩ

300

ns

1.216 1.235 1.254

V

-50

±1

+50

nA

20

µs

Note 1: Production testing done at TA = +25°C. Over temperature limits are guaranteed by design.

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