MAX5500AGAP Просмотр технического описания (PDF) - Maxim Integrated

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MAX5500AGAP

Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface

Maxim Integrated 

Low-Power, Quad, 12-Bit

Voltage-Output DACs with Serial Interface

ELECTRICAL CHARACTERISTICS (continued)

(MAX5500 (VDD = +5V ±10%, VREFAB = VREFCD = 2.5V), MAX5501 (VDD = +3V to +3.6V, VREFAB = VREFCD = 1.25V), VAGND = VDGND

= 0, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25°C. Output buffer connected in

unity-gain configuration (Figure 9).)

PARAMETER

SYMBOL

CONDITIONS

DIGITAL OUTPUTS

Output High Voltage

Output Low Voltage

DYNAMIC PERFORMANCE

VOH

VOL

ISOURCE = 2mA

ISINK = 2mA

Voltage Output Slew Rate

SR

Output Settling Time

To ±0.5 LSB, VSTEP = 2.5V

MAX5500A/MAX5500B

To ±0.5 LSB, VSTEP = 1.25V

MAX5501A/MAX5501B

Output Voltage Swing

Current into FB_

Rail-to-rail (Note 2)

OUT_ Leakage Current in

Shutdown

RL = ∞

Startup Time Exiting

Shutdown Mode

Digital Feedthrough

Digital Crosstalk

POWER SUPPLIES

Supply Voltage

VDD

Supply Current

IDD

Supply Current in Shutdown

TIMING CHARACTERISTICS (Figure 6)

SCLK Clock Period

tCP

SCLK Pulse-Width High

tCH

SCLK Pulse-Width Low

tCL

CS Fall to SCLK Rise Setup

Time

tCSS

MAX5500A/MAX5500B

MAX5501A/MAX5501B

CS =VDD, fIN = 100kHz

MAX5500A/MAX5500B

MAX5501A/MAX5501B

(Note 3)

(Note 3)

SCLK Rise to CS Rise Hold

Time

tCSH

DIN Setup Time

tDS

DIN Hold Time

tDH

MIN

TYP

MAX

UNITS

VDD - 0.5

V

0.13

0.4

V

0.6

12

16

0 to VDD

0

±0.01

15

20

5

5

0.1

±1.0

V/µs

µs

V

µA

µA

µs

nV•s

nV•s

4.5

5.5

V

3.0

3.6

0.85

1.1

mA

10

20

µA

100

ns

40

ns

40

ns

40

ns

0

ns

40

ns

0

ns

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