MAX17040 Просмотр технического описания (PDF) - Maxim Integrated

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MAX17040

1-Cell/2-Cell Fuel Gauge with ModelGauge

Maxim Integrated 

MAX17040/MAX17041

1-Cell/2-Cell Fuel Gauge with ModelGauge

Bit Transfer

One data bit is transferred during each SCL clock cycle,

with the cycle defined by SCL transitioning low to high and

then high to low. The SDA logic level must remain stable

during the high period of the SCL clock pulse. Any change

in SDA when SCL is high is interpreted as a START or

STOP control signal.

Bus Idle

The bus is defined to be idle, or not busy, when no master

device has control. Both SDA and SCL remain high when

the bus is idle. The STOP condition is the proper method

to return the bus to the idle state.

START and STOP Conditions

The master initiates transactions with a START condition

(S) by forcing a high-to-low transition on SDA while SCL

is high. The master terminates a transaction with a STOP

condition (P), a low-to-high transition on SDA while SCL

is high. A Repeated START condition (Sr) can be used in

place of a STOP then START sequence to terminate one

transaction and begin another without returning the bus to

the idle state. In multimaster systems, a Repeated START

allows the master to retain control of the bus. The START

and STOP conditions are the only bus activities in which

the SDA transitions when SCL is high.

Acknowledge Bits

Each byte of a data transfer is acknowledged with an

Acknowledge bit (A) or a No-Acknowledge bit (N). Both

the master and the MAX17040 slave generate acknowl-

edge bits. To generate an acknowledge, the receiving

device must pull SDA low before the rising edge of the

acknowledge-related clock pulse (ninth pulse) and keep it

low until SCL returns low. To generate a no acknowledge

(also called NAK), the receiver releases SDA before the

rising edge of the acknowledge-related clock pulse and

leaves SDA high until SCL returns low. Monitoring the

Acknowledge bits allows for detection of unsuccessful

data transfers. An unsuccessful data transfer can occur

if a receiving device is busy or if a system fault has

occurred. In the event of an unsuccessful data transfer,

the bus master should reattempt communication.

Data Order

A byte of data consists of 8 bits ordered most significant

bit (MSb) first. The least significant bit (LSb) of each

byte is followed by the Acknowledge bit. The MAX17040/

MAX17041 registers composed of multibyte values are

ordered MSB first. The MSB of multibyte registers is

stored on even data-memory addresses.

Slave Address

A bus master initiates communication with a slave device

by issuing a START condition followed by a Slave Address

(SAddr) and the Read/Write (R/W) bit. When the bus is

idle, the MAX17040/MAX17041 continuously monitor for

a START condition followed by its Slave Address. When

the MAX17040/MAX17041 receive a Slave Address

that matches the value in the Slave Address Register, it

responds with an Acknowledge bit during the clock period

following the R/W bit. The 7-bit slave address is fixed to

6Ch (write)/6DH (read):

MAX17040/MAX17041

SLAVE ADDRESS

0110110

Read/Write Bit

The R/W bit following the slave address determines the

data direction of subsequent bytes in the transfer. R/W = 0

selects a write transaction, with the following bytes being

written by the master to the slave. R/W = 1 selects a read

transaction, with the following bytes being read from the

slave by the master.

Bus Timing

The MAX17040/MAX17041 are compatible with any bus

timing up to 400kHz. No special configuration is required

to operate at any speed.

2-Wire Command Protocols

The command protocols involve several transaction for-

mats. The simplest format consists of the master writing

the START bit, slave address, R/W bit, and then monitor-

ing the Acknowledge bit for presence of the MAX17040/

MAX17041. More complex formats, such as the Write

Data and Read Data, read data and execute device-

specific operations. All bytes in each command format

require the slave or host to return an Acknowledge bit

before continuing with the next byte. Table 5 shows the

key that applies to the transaction formats.

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