M81019FP Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

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M81019FP

1200V HIGH VOLTAGE HALF BRIDGE DRIVER

MITSUBISHI ELECTRIC  

MITSUBISHI SEMICONDUCTORS <HVIC>

M81019FP

1200V HIGH VOLTAGE HALF BRIDGE DRIVER

2. INPUT INTERLOCK TIMING DIAGRAM

When the input signals (HIN/LIN) are high level at the same time, the outputs (HOUT/LOUT) keep their previous status.

But if signals (HIN/LIN) are going to high level simultaneously, HIN signals will get active and cause HOUT to enter “H” status.

HIN

LIN

HOUT

LOUT

Note1: The minimum input pulse width at HIN/LIN should be to more than 500ns (because of HIN/LIN input noise filter circuit).

Note2: If a high-high status of input signals (HIN/LIN) is ended with only one input signal entering low level and another still being in high level, the output will

enter high-low status after the delay match time (not shown in the figure above).

Note3: Delay times between input and output signals are not shown in the figure above.

3. SHORT CIRCUIT PROTECTION TIMING DIAGRAM

When an over-current is detected by exceeding the threshold at the CIN and LIN is at high level at the same time, the

short circuit protection will get active and shutdown the outputs while FO will issue a low level (indicating a fault signal).

The fault output latch is reset by a high level signal at FO_RST pin and then FO will return to high level while the output

of the driver will respond to the following active input signal.

HIN

LIN

CIN

FO_RST

HOUT

LOUT

FO

Note1 : Delay times between input and output signals are not shown in the figure above.

Note2 : The minimum FO_RST pulse width should be more than 500ns (because of FO_RST input filter circuit).

6

Aug. 2009

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