M5M51008KR-55H Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC
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M5M51008KR-55H Datasheet PDF : 8 Pages
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Ver. 1.1
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, 5V±10% unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Input pulse level ............... VIH=2.4V,VIL=0.6V (-70H)
VIH=3.0V,VIL=0.0V (-55H)
Input rise and fall time ...... 5ns
Reference level ................ VOH=VOL=1.5V
Output loads..................... Fig.1, CL=100pF (-70H)
CL=30pF (-55H)
CL=5pF (for ten,tdis)
Transition is measured ± 500mV from steady
state voltage. (for ten,tdis)
VCC
1.8kΩ
DQ
990Ω
CL ( Including scope
and JIG )
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S1)
ta(S2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(OE)
ten(S1)
ten(S2)
ten(OE)
tV(A)
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S1 high
Output disable time after S2 low
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after OE low
Data valid time after address
Limits
-55H
-70H
Unit
Min Max Min Max
55
70
ns
55
70
ns
55
70
ns
55
70
ns
30
35
ns
20
25
ns
20
25
ns
20
25
ns
5
10
ns
5
10
ns
5
5
ns
5
10
ns
(3) WRITE CYCLE
Symbol
Parameter
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S1)
tsu(S2)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
Limits
-55H
-70H
Unit
Min Max Min Max
55
70
ns
45
50
ns
0
0
ns
50
55
ns
50
55
ns
50
55
ns
25
30
ns
0
0
ns
0
0
ns
20
25
ns
20
25
ns
5
5
ns
5
5
ns
MITSUBISHI
ELECTRIC
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