M48TMH1 Просмотр технического описания (PDF) - STMicroelectronics

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производитель

M48TMH1

5V PC REAL TIME CLOCK

STMicroelectronics 

M48T86

Figure 4. Block Diagram

OSCILLATOR

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E

VCC

VBAT

POWER

SWITCH

AND

WRITE

PROTECT

VCC

POK

PERIODIC INTERRUPT/SQUARE WAVE SELECTOR

CLOCK/

CALENDAR

UPDATE

SQUARE WAVE

OUTPUT

REGISTERS A,B,C,D

SQW

IRQ

RST

CLOCK CALENDAR,

AND ALARM RAM

DOUBLE

BUFFERED

DS

R/W

AS

AD0-AD7

BUS

INTERFACE

BCD/BINARY

INCREMENT

STORAGE

REGISTERS

(114 BYTES)

RCL

AI01643

DS (Data Strobe Input). The DS pin is also re-

ferred to as Read (RD). A falling edge transition on

the Data Strobe (DS) input enables the output dur-

ing a a read cycle. This is very similar to an Output

Enable (G) signal on other memory devices.

E (Chip Enable Input). The Chip Enable pin

must be asserted low for a bus cycle in the

M48T86 to be accessed. Bus cycles which take

place without asserting E will latch the addresses

present, but no data access will occur.

IRQ (Interrupt Request Output). The IRQ pin is

an open drain output that can be used as an inter-

rupt input to a processor. The IRQ output remains

low as long as the status bit causing the interrupt

is present and the corresponding interrupt-enable

bit is set. IRQ returns to a high impedance state

whenever Register C is read. The RST pin can

also be used to clear pending interrupts. Because

the IRQ bus is an open drain output, it requires an

external pull-up resistor to VCC.

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