LC78602NE Просмотр технического описания (PDF) - SANYO -> Panasonic
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LC78602NE Datasheet PDF : 11 Pages
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LC78602NE
Continued from preceding page.
Pin No.
49
Pin
EFLG
50
FSX
51
*AMUTE
52
REMOTE
53
RMTSL2
54
LCHO
55
L/RVDD
56
L/RVSS
57
RCHO
58
CLOSE
59
RMTSL1
60
XOUT
61
XIN
62
XVDD
63
*RES
64
DRF
I/O
Function
Monitor for C1, C2, single, and double error corrections.
O (Note that this output is only provided in test mode. This pin outputs a low level during normal
mode operation.)
Outputs a 7.35 kHz synchronizing signal that is generated by dividing the crystal oscillator output.
O (Note that this output is only provided in test mode. This pin outputs a low level during normal
mode operation.)
O Audio mute output signal
I Remote controller signal input
Remote controller identifier input (2). This pin functions as an output pin set to the low level
during resets (when the *RES pin is low) and for a few milliseconds after the *RES pin
I/O switches to the high level. Therefore, applications that will set this pin high must connect an
external pull-up resistor to this pin.
O Left channel D/A converter output
— D/A converter power supply
— D/A converter ground. This pin must be connected to 0 V.
O Right channel D/A converter output
I Close switch detection input. A pull-up resistor is built in.
I Remote controller identifier input (1). A pull-up resistor is built in.
O
Connections for a 16.9344 crystal element
I
— Crystal oscillator circuit power supply
I IC reset input. Applications must set this pin low temporarily when power is first applied.
I DRF input
Note: The same potential must be connected to all the power supply pins (VDD, VVDD, L/RVDD, and XVDD).
Pin state during reset
Low output
Low output
Low output
—
Low output
Undefined
—
—
Undefined
—
—
Clock output
—
—
—
No. 6021-7/11
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