KSZ8863MLL Просмотр технического описания (PDF) - Micrel

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производитель

KSZ8863MLL

Integrated 3-Port 10/100 Managed Switch with PHYs

Micrel 

Micrel, Inc.

KSZ8863MLL/FLL//RLL

List of Tables

Table 1. FX Signal Threshold............................................................................................................................................... 18

Table 2. MDI/MDI-X Pin Definitions ..................................................................................................................................... 19

Table 3. Internal Function Block Status ................................................................................................................................ 23

Table 4. MII Signals ............................................................................................................................................................. 29

Table 5. RMII Clock Setting .................................................................................................................................................. 30

Table 6. RMII Signal Description.......................................................................................................................................... 31

Table 7. RMII Signal Connections........................................................................................................................................ 32

Table 8. MII Management Interface Frame Format ............................................................................................................. 32

Table 9. Serial Management Interface (SMI) Frame Format ............................................................................................... 33

Table 10. FID+DA Lookup in VLAN Mode ........................................................................................................................... 34

Table 11. FID+SA Lookup in VLAN Mode ........................................................................................................................... 34

Table 12. Spanning Tree States .......................................................................................................................................... 36

Table 13. SPI Connections .................................................................................................................................................. 41

Table 14. Data Rate Limit Table .......................................................................................................................................... 62

Table 16. Format of Static VLAN Table (16 Entries)............................................................................................................ 86

Table 17. Format of Dynamic MAC Address Table (1K Entries) ......................................................................................... 87

Table 18. Format of “Per Port” MIB Counters ...................................................................................................................... 88

Table 19. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets.................................................................................. 89

Table 20. Format of “All Port Dropped Packet” MIB Counters............................................................................................. 90

Table 21. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets...................................................................... 90

Table 22. EEPROM Timing Parameters .............................................................................................................................. 94

Table 23. MAC Mode MII Timing Parameters...................................................................................................................... 95

Table 24. PHY Mode MII Timing Parameters ...................................................................................................................... 96

Table 25. RMII Timing Parameters ...................................................................................................................................... 97

Table 26. I2C Timing Parameters......................................................................................................................................... 99

Table 27. SPI Input Timing Parameters ............................................................................................................................. 100

Table 28. SPI Output Timing Parameters .......................................................................................................................... 101

Table 29. Auto-Negotiation Timing Parameters................................................................................................................. 102

Table 30. MDC/MDIO Timing Parameters ......................................................................................................................... 103

Table 32. Transformer Selection Criteria ........................................................................................................................... 106

Table 33. Qualified Single Port Magnetics ......................................................................................................................... 106

Table 34. Typical Reference Crystal Characteristics ......................................................................................................... 106

January 27, 2014

11

Revision 1.5

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