IA6805E2-PDW40I-00 Просмотр технического описания (PDF) - InnovASIC, Inc
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IA6805E2-PDW40I-00 Datasheet PDF : 33 Pages
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IA6805E2
Microprocessor Unit
As of Production Version 00
29 August 2007
AS
DS
ADD_BUS_UNMUX[8:12]
IRQ_N__TCR7_N
n0
n1
n2
n3
n4
n5
n6
n7
n8
n9
NEXT OP CODE ADDRESS
T ILASL
1F (FF) 1F (FF)
(NOTE)
T DSLIH
INT ROUTINE
INT ROUTINE
LAST ADDRESS
STARTING ADDRESS
MUX_ADD_DATA[0:7]
SP PCL SP-1 PCH SP-2 X SP-3 A SP-4 CC
NEW PCH
NEW PCL
NEXT OP CODE
FA (IRQ) FB (IRQ) 1ST OP
F8 (TIMER) F9 (TIMER) INT ROUTINE
80
RTI
OP CODE
RW_N
Note: tDSLIH- the interrupting device must release the IRQ_N line within this time to prevent subsequent recognition
of the same interrupt.
Figure 15. IRQ_n and TCR7_N Interrupt Timing
Figure 16. Power-On-Reset and RESET_n Timing
Copyright © 2007
©
IA211081401-03
Page 27 of 33
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