IA6805E2-PDW40I-00 Просмотр технического описания (PDF) - InnovASIC, Inc
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IA6805E2-PDW40I-00 Datasheet PDF : 33 Pages
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IA6805E2
Microprocessor Unit
As of Production Version 00
29 August 2007
Control Timing
VSS=0V, TA=TL to TH
VDD = 5.0V ±10%
fOSC = 5MHz
Parameters
Sym Min Typ Max Unit
I/O Port Timing – Input Setup Time tPVASL 196 -
(Figure 14)
-
ns
Input Hold Time (Figure 14)
tASLPX
0
-
-
ns
Output Delay Time (Figure 14)
tASLPV
-
-
0
ns
Interrupt Setup Time (Figure 15)
TILASL 0.4
-
-
μs
Crystal Oscillator Startup Time
(Figure 16)
tOXOV
-
5 100 ms
Wait Recovery Startup Time (Figure tIVASH -
-
2
μs
17)
Stop Recovery Startup Time
(Figure 18)
tILASH
-
-
2
μs
Required Interrupt Release (Figure 15) tDSLIH -
-
1.0 μs
Timer Pulse Width (Figure 17)
tTH, tTL 0.5
-
-
tCYC
Reset Pulse Width (Figure 16)
tRL 1.05 -
-
μs
Timer Period (Figure 17)
tTLTL 1.0
-
-
tCYC
Interrupt Pulse Width Low (Figure10) tILIH 1.0 -
-
tCYC
Interrupt Pulse Period
(Figure 10)
tILIL
*
-
-
tCYC
Oscillator Cycle Period
(1/5 of tCYC) (Figure 3)
tOLOL 200
-
-
ns
OSC1 Pulse Width High (Figure 3)
tOH
75
-
-
ns
OSC1 Pulse Width Low (Figure 3)
tOL
75
-
-
ns
*The minimum period of tILIL should not be less than the number of tCYC cycles it takes to execute the
interrupt service routine plus 20 tCYC cycles.
Copyright © 2007
©
IA211081401-03
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