F81216 Просмотр технического описания (PDF) - Feature Integration Technology Inc.

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F81216

LPC to 4 UART

Feature Integration Technology Inc. 

F81216

4. Pin Description

I/O8t5V-d100 - TTL level bi-directional pin with 8 mA source-sink capability, 5V tolerance, pull-down

100K ohms

I/O12t

- TTL level bi-directional pin with 12 mA source-sink capability

I/OD12

- TTL level bi-directional pin, Open-drain outpu with 12 mA sink capability

PCI5V

OUT12

- bi-direction pin, slew rate control, 5V tolerance.

- Output pin with 12 mA source-sink capability

OD12

- Open-drain output pin with 12 mA sink capability

INt

- TTL level input pin

INt5V

- TTL level input pin and 5V tolerance.

INts

INts5V

- TTL level input pin and schmitt trigger

- TTL level input pin and Schmitt trigger, 5V tolerance.

P

- Power

4.1 ISA/LPC Interface

Pin No. Pin Name

1

PCIRST#

2

WDT_OUT#

4~7

LPC_LAD[3:0]

8

LCLK

9

FRAME#

10

SERIRQ

12

CLKIN

Type

INts

OD12

PCI5V

INts5V

INts5V

PCI5V

INt5V

Description

System PCI reset active low.

Watch dog timer output. When pin 24 power on setting

PS_WDT=0(default), Watch Dog timer time interval setting is

programmed by register. Once power on setting PS_WDT=1,

watch dog timer time interval will be fixed to 10 sec.

When in LPC mode, these signal lines communicate address,

control, and data information over the LPC bus between a host

and a peripheral.

In LPC mode, this pin acts as PCI clock input.

In LPC mode, indicates start of a new cycle or termination of a

broken cycle.

In LPC mode, Serial IRQ input/Output.

Clock Input

-3-

August, 2007

V0.32P

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