DS24B33 Просмотр технического описания (PDF) - Maxim Integrated

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DS24B33

4Kb 1-Wire EEPROM with 200k Write/Erase Cycles

Maxim Integrated 

4Kb 1-Wire EEPROM with

200k Write/Erase Cycles

The shift register bits are initialized to 0. Then, starting

with the LSB of the family code, one bit at a time is

shifted in. After the 8th bit of the family code has been

entered, the serial number is entered. After the last bit

of the serial number has been entered, the shift register

contains the CRC value. Shifting in the 8 bits of the

CRC returns the shift register to all 0s.

Memory

The DS24B33 EEPROM array (Figure 5) consists of 16

pages of 32 bytes each, starting at address 0000h and

ending at address 01FFh. In addition to the EEPROM,

the device has a 32-byte volatile scratchpad. Writes to

the EEPROM array are a two-step process. First, data

is written to the scratchpad and then copied into the

main array. The user can verify the data in the scratch-

pad prior to copying.

POLYNOMIAL = X8 + X5 + X4 + 1

1ST

STAGE

2ND

STAGE

3RD

STAGE

4TH

STAGE

X0

X1

X2

X3

Figure 4. 1-Wire CRC Generator

5TH

STAGE

X4

6TH

STAGE

7TH

STAGE

8TH

STAGE

X5

X6

X7

X8

INPUT DATA

ADDRESS

0000h to 001Fh

0020h to 003Fh

0040h to 01DFh

01E0h to 01FFh

Figure 5. Memory Map

32-BYTE INTERMEDIATE STORAGE SCRATCHPAD

32-BYTE FINAL STORAGE EEPROM

32-BYTE FINAL STORAGE EEPROM

FINAL STORAGE EEPROM

32-BYTE FINAL STORAGE EPPROM

PAGE 0

PAGE 1

PAGES 2 to 14

PAGE 15

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