NM25C160TLZET8 Просмотр технического описания (PDF) - Fairchild Semiconductor
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производитель
NM25C160TLZET8
Fairchild Semiconductor
NM25C160TLZET8 Datasheet PDF : 10 Pages
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Low Voltage 2.7V ≤ VCC ≤ 4.5V Specifications
Absolute Maximum Ratings (Note 5)
Operating Conditions
Ambient Storage Temperature
All Input or Output Voltage with
Respect to Ground
Lead Temp. (Soldering, 10 sec.)
ESD Rating
-65°C to +150°C
+6.5V to -0.3V
+300°C
2000V
Ambient Operating Temperature
NM25C160L/LZ
NM25C160LZ/LZE
NM25C160LV
Power Supply (VCC)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
2.7V–4.5V
DC and AC Electrical Characteristics 2.7V ≤ VCC ≤ 4.5V (unless otherwise specified)
25C160L/LE
25C160LV
25C160LZ/LZE
Symbol Parameter
Part
Conditions Min. Max. Min Max Units
ICC
ICCSB
Operating Current
Standby Current
CS = VIL
L
CS = VCC
LZ
3
3
mA
10
10
µA
1
N/A
µA
IIL
Input Leakage
VIN = 0 to VCC
-1
1
-1
1
µA
IOL
Output Leakage
VOUT = GND to VCC
-1
1
-1
1
µA
VIL
Input Low Voltage
-0.3
VCC * 0.3
-0.3
VCC * 0.3
V
VIH
Input High Voltage
0.7 * VCC VCC + 0.3 0.7 * VCC VCC + 0.3
V
VOL
Output Low Voltage
IOL = 0.8 mA
0.4
0.4
V
VOH
Output High Voltage
IOH = –0.8 mA
VCC - 0.8
VCC - 0.8
V
fOP
SCK Frequency
1.0
1.0
MHz
tRI
Input Rise Time
2.0
2.0
µs
tFI
Input Fall Time
2.0
2.0
µs
tCLH
Clock High Time
(Note 6)
410
410
ns
tCLL
Clock Low Time
(Note 6)
410
410
ns
tCSH
Min. CS High Time
(Note 7)
500
500
ns
tCSS
CS Setup Time
500
500
ns
tDIS
Data Setup Time
100
100
ns
tHDS
HOLD Setup Time
240
240
ns
tCSN
CS Hold Time
500
500
ns
tDIN
Data Hold Time
100
100
ns
tHDN
HOLD Hold Time
240
240
ns
tPD
Output Delay
CL = 200 pF
500
500
ns
tDH
Output Hold Time
0
0
ns
tLZ
HOLD Output Low Z
240
240
ns
tDF
Output Disable Time
CL = 200 pF
500
500
ns
tHZ
HOLD to Output Hi Z
240
240
ns
tWP
Write Cycle Time
1-16 Bytes
15
15
ms
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 8) AC Test Conditions
Symbol
COUT
Test
Typ Max Units
Output Capacitance
3
8 pF
Output Load
Input Pulse Levels
IOL = 10 µA, IOH = 10 µA
0.3V to 3.5V
Timing Measurement Reference Level
CIN
Input Capacitance
2
6 pF
Input
0.4V and 1.6V
Output
0.8V and 1.6V
Note 5: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Note 6: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns.
Note 7: CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 8: This parameter is periodically sampled and not 100% tested.
NM25C160 Rev. D.1
4
www.fairchildsemi.com
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