CY7C056V-20BAI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C056V-20BAI Datasheet PDF : 22 Pages
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PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[27, 28, 29, 30]
tWC
ADDRESS
OE
CE0, CE1[31, 32]
R/W
DATA OUT
DATA IN
tAW
CHIP SELECT VALID
tSA
tPWE[30]
NOTE 34
tHZWE[33]
tSD
CY7C056V
CY7C057V
tHZOE[33]
tHA
tLZWE
tHD
NOTE 34
Write Cycle No. 2: CE Controlled Timing[27, 28, 29, 35]
tWC
ADDRESS
CE0, CE1[31, 32]
tSA
R/W
tAW
CHIP SELECT VALID
tSCE
tSD
DATA IN
tHA
tHD
Notes:
27. R/W must be HIGH during all address transitions.
28. A write occurs during the overlap (tSCE or tPWE) of CE0=VIL and CE1=VIH or SEM=VIL and B0–3 LOW.
29. tHA is measured from the earlier of CE0/CE1 or R/W or (SEM or R/W) going HIGH at the end of Write Cycle.
30. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE.
31. To access RAM, CE0 = VIL, CE1=SEM = VIH.
32. To access byte B0, CE0 = VIL, B0 = VIL, CE1=SEM = VIH.
To access byte B1, CE0 = VIL, B1 = VIL, CE1=SEM = VIH.
To access byte B2, CE0 = VIL, B2 = VIL, CE1=SEM = VIH.
To access byte B3, CE0 = VIL, B3 = VIL, CE1=SEM = VIH.
33. Transition is measured ±150 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. During this period, the I/O pins are in the output state, and input signals must not be applied.
35. If the CE0 LOW and CE1 HIGH or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
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