CY7C056V-20AI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C056V-20AI Datasheet PDF : 22 Pages
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PRELIMINARY
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[22, 23, 24]
tRC
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
CY7C056V
CY7C057V
DATA VALID
tOHA
Read Cycle No. 2 (Either Port CE/OE Access)[22, 25, 26]
tACE
CE0, CE1, B0,B1,
B2, B3, WA, BA
OE
SELECT VALID
tDOE
DATA OUT
ICC
CURRENT
I
SB
tLZOE
tLZCE
tPU
Read Cycle No. 3 (Either Port)[22, 24, 25, 26]
tRC
ADDRESS
tAA
B0, B1, B2,
B3, WA, BA
CE0, CE1
BYTE SELECT VALID
tLZCE
tABE
CHIP SELECT VALID
DATA OUT
tACE
tLZCE
tHZCE
tHZOE
DATA VALID
tPD
tOHA
tHZCE
tHZCE
Notes:
22. R/W is HIGH for read cycles.
23. Device is continuously selected. CE0 = VIL, CE1=VIH, and B0, B1, B2, B3, WA, BA are valid. This waveform cannot be used for semaphore reads.
24. OE = VIL.
25. Address valid prior to or coinciding with CE0 transition LOW and CE1 transition HIGH.
26. To access RAM, CE0 = VIL, CE1=VIH, B0, B1, B2, B3, WA, BA are valid, and SEM = VIH. To access semaphore, CE0 = VIH, CE1=VIL and SEM = VIL or CE0 and SEM=VIL,
and CE1= B0 = B1 = B2 = B3, =VIH.
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