X24164P Просмотр технического описания (PDF) - Xicor -> Intersil

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X24164P

Serial E2PROM

Xicor -> Intersil 

X24164

DEVICE OPERATION

The X24164 supports a bidirectional bus oriented proto-

col. The protocol defines any device that sends data onto

the bus as a transmitter, and the receiving device as the

receiver. The device controlling the transfer is a master

and the device being controlled is the slave. The master

will always initiate data transfers, and provide the clock for

both transmit and receive operations. Therefore, the

X24164 will be considered a slave in all applications.

Figure 1. Data Validity

Clock and Data Conventions

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are re-

served for indicating start and stop conditions. Refer to

Figures 1 and 2.

Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL is

HIGH. The X24164 continuously monitors the SDA and

SCL lines for the start condition and will not respond to

any command until this condition has been met.

SCL

SDA

DATA STABLE DATA

CHANGE

3846 FHD F07

Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V)

(6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the

device requires to perform the internal write operation.

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT

STOP BIT

3846 FHD F08

3

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