Clock Timing Conditions of Panel Block
Item
HST rise time
HST fall time
HST
HST data setup time
HCK
HST data hold time
HCKn∗5 rise time
HCKn∗5 fall time
HCK1 fall to HCK2 rise time
HCK1 rise to HCK2 fall time
VST rise time
VST fall time
VST
VST data setup time
VST data hold time
VCK rise time
VCK
VCK fall time
EN rise time
EN fall time
EN
EN fall to VCK rise/fall time
EN pulse width
WIDE rise time
WIDE fall time
WIDE
WIDE (H) rise to VCK rise/fall time
WIDE (H) pulse width
∗5 HCKn means HCK1 and HCK2. (fHCKn = 1.5MHz)
ACX306BKM
(VIH = 3.0V, VDD = 12V, Ta = 25°C)
Symbol
trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
tfVst
tdVst
thVst
trVckn
tfVckn
trEn
tfEn
tdEn
twEn
trWide
tfWide
tdhWide
twhWide
Min.
—
—
300
–30
—
—
–15
–15
—
—
30
–30
—
—
—
—
500
2900
—
—
–0.4
1.4
Typ.
—
—
333
0
—
—
0
0
—
—
32
–32
—
—
—
—
600
3000
—
—
–0.5
1.5
Max. Unit
30
30
363
30
30
ns
30
15
15
100
100
34
µs
–34
100
100
100
100
ns
700
3100
100
100
–0.6
µs
1.6
–8–