AD9364 Просмотр технического описания (PDF) - Analog Devices

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производитель

AD9364

RF Agile Transceiver

Analog Devices 

Data Sheet

AD9364

Parameter1

Symbol Min

Typ

Max

Bus Turnaround Time

Before Rx

tRPRE

2 × tCP

After Rx

tRPST

2 × tCP

Capacitive Load

3

Capacitive Input

3

SUPPLY CHARACTERISTICS

1.3 V Main Supply Voltage

1.267

1.3

1.33

VDD_INTERFACE Supply

Nominal Settings

CMOS

1.14

2.625

LVDS

1.71

2.625

VDD_INTERFACE Tolerance

−5

+5

VDD_GPO Supply Nominal

1.3

3.3

Setting

VDD_GPO Tolerance

−5

+5

Current Consumption

VDDx, Sleep Mode

180

VDD_GPO

50

Unit

Test Conditions/Comments

ns

ns

pF

pF

V

V

V

%

Tolerance is applicable to

any voltage setting

V

When unused, must be set

to 1.3 V

%

Tolerance is applicable to

any voltage setting

μA

Sum of all input currents

μA

No load

1 When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin

names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.

CURRENT CONSUMPTION—VDD_INTERFACE

Table 2. VDD_INTERFACE = 1.2 V

Parameter

SLEEP MODE

RX AND TX, DOUBLE DATA RATE (DDR)

LTE 10 MHz

Single Port

Dual Port

LTE 20 MHz

Dual Port

Min Typ

45

2.9

2.7

5.2

Max

Unit

Test Conditions/Comments

μA

Power applied, device disabled

mA

30.72 MHz data clock, CMOS

mA

15.36 MHz data clock, CMOS

mA

30.72 MHz data clock, CMOS

Table 3. VDD_INTERFACE = 1.8 V

Parameter

SLEEP MODE

RX AND TX, DDR

LTE 10 MHz

Single Port

Dual Port

LTE 20 MHz

Dual Port

Min

Typ

Max

Unit

Test Conditions/Comments

84

μA

Power applied, device disabled

4.5

mA

30.72 MHz data clock, CMOS

4.1

mA

15.36 MHz data clock, CMOS

8.0

mA

30.72 MHz data clock, CMOS

Table 4. VDD_INTERFACE = 2.5 V

Parameter

SLEEP MODE

RX AND TX, DDR

LTE 10 MHz

Single Port

Dual Port

LTE 20 MHz

Dual Port

Min

Typ

Max

Unit

Test Conditions/Comments

150

μA

Power applied, device disabled

6.5

mA

30.72 MHz data clock, CMOS

6.0

mA

15.36 MHz data clock, CMOS

11.5

mA

30.72 MHz data clock, CMOS

Rev. C | Page 7 of 32

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