AD9364 Просмотр технического описания (PDF) - Analog Devices
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производитель
AD9364 Datasheet PDF : 32 Pages
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AD9364
Parameter1
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 1.8 V
DATA_CLK Clock Period
DATA_CLK and FB_CLK Pulse
Width
Tx Data
Setup to FB_CLK
Hold to FB_CLK
DATA_CLK to Data Bus Output
Delay
DATA_CLK to RX_FRAME
Delay
Pulse Width
ENABLE
TXNRX
Symbol Min
tCP
16.276
tMP
45% of tCP
tSTX
1
tHTX
0
tDDRX
0
tDDDV
0
tENPW
tCP
tTXNRXPW tCP
TXNRX Setup to ENABLE
Bus Turnaround Time
Before Rx
After Rx
Capacitive Load
Capacitive Input
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 2.5 V
DATA_CLK Clock Period
DATA_CLK and FB_CLK Pulse
Width
Tx Data
Setup to FB_CLK
Hold to FB_CLK
DATA_CLK to Data Bus Output
Delay
DATA_CLK to RX_FRAME
Delay
Pulse Width
ENABLE
TXNRX
tTXNRXSU
tRPRE
tRPST
tCP
tMP
tSTX
tHTX
tDDRX
tDDDV
tENPW
tTXNRXPW
0
2 × tCP
2 × tCP
16.276
45% of tCP
1
0
0
0
tCP
tCP
TXNRX Setup to ENABLE
Bus Turnaround Time
Before Rx
After Rx
Capacitive Load
Capacitive Input
DIGITAL DATA TIMING (LVDS)
DATA_CLK Clock Period
DATA_CLK and FB_CLK Pulse
Width
Tx Data
Setup to FB_CLK
Hold to FB_CLK
DATA_CLK to Data Bus Output
Delay
DATA_CLK to RX_FRAME
Delay
Pulse Width
ENABLE
TXNRX
tTXNRXSU
tRPRE
tRPST
tCP
tMP
tSTX
tHTX
tDDRX
tDDDV
tENPW
tTXNRXPW
0
2 × tCP
2 × tCP
4.069
45% of tCP
1
0
0.25
0.25
tCP
tCP
TXNRX Setup to ENABLE
tTXNRXSU 0
Typ
Max
55% of tCP
1.5
1.0
3
3
55% of tCP
1.2
1.0
3
3
55% of tCP
1.25
1.25
Rev. C | Page 6 of 32
Data Sheet
Unit
Test Conditions/Comments
ns
61.44 MHz
ns
TX_FRAME, P0_D, and P1_D
ns
ns
ns
ns
ns
ns
FDD independent ENSM
mode
ns
TDD ENSM mode
ns
TDD mode
ns
TDD mode
pF
pF
ns
61.44 MHz
ns
TX_FRAME, P0_D, and P1_D
ns
ns
ns
ns
ns
ns
FDD independent ENSM
mode
ns
TDD ENSM mode
ns
TDD mode
ns
TDD mode
pF
pF
ns
245.76 MHz
ns
TX_FRAME and TX_D
ns
ns
ns
ns
ns
ns
FDD independent ENSM
mode
ns
TDD ENSM mode
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