X88C64 Просмотр технического описания (PDF) - Xicor -> Intersil
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X88C64 Datasheet PDF : 14 Pages
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X88C64
TOGGLE BIT POLLING
Because the X88C64 typical nonvolatile write cycle time
is less than the specified 5ms, Toggle Bit Polling has
been provided to determine the early completion of
write. During the internal programming cycle I/O6 will
toggle from HIGH to LOW and LOW to HIGH on subse-
Toggle Bit Polling RD/WR Control
quent attempts to read the device. When the internal
cycle is complete, the toggling will cease and the device
will be accessible for additional read or write operations.
Due to the dual plane architecture, reads for polling
must occur in the plane that was written; that is, the state
of A12 during a write must match the state of A12 during
Toggle Bit Polling.
OPERATION
LAST BYTE
WRITTEN
CE
ALE
A/D0–A/D7
A8–A12
AIN DIN
A12=n
WR
RD
I/O6=X
I/O6=X
I/O6=X
I/O6=X
X88C64 READY FOR
NEXT OPERATION
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=x
AIN
ADDR
3867 FHD F09
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
6
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