X88C64 Просмотр технического описания (PDF) - Xicor -> Intersil

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X88C64

E2 Micro-Peripheral

Xicor -> Intersil 

X88C64

PAGE WRITE OPERATION

Regardless of the microcontroller employed, the X88C64

supports page mode write operations. This allows the

microcontroller to write from one to thirty-two bytes of

data to the X88C64. Each individual write within a page

write operation must conform to the byte write timing

requirements. The falling edge of WR starts a timer

delaying the internal programming cycle 100µs. There-

fore, each successive write operation must begin within

100µs of the last byte written. The following waveforms

illustrate the sequence and timing requirements.

Page Write Timing Sequence for WR Controlled Operation

OPERATION

BYTE 0

BYTE 1

BYTE 2

LAST BYTE

READ (1)(2)

AFTER tWC READY FOR

NEXT WRITE OPERATION

CE

ALE

A/D0–A/D7

AIN DIN

AIN DIN

AIN DIN

AIN DIN

AIN DOUT

AIN

AIN

A8–A12

A12=n

A12=n

A12=n

A12=n

A12=x

ADDR

Next Address

WR

PSEN(RD)

tBLC

tWC

3867 FHD F08

Notes: (1) For each successive write within a page write cycle A5–A12 must be the same.

(2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page

write operation. Two responses are possible:

a. Reading from the same plane being written (A12 of Read = A12 of Write) is effectively a Toggle Bit Polling operation.

b. Reading from the opposite plane being written (A12 of Read ≠ A12 of Write) true data will be returned, facilitating the use of a

single memory component as both program and data storage.

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