X25170AEG Просмотр технического описания (PDF) - IC MICROSYSTEMS

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X25170AEG

SPI Serial E 2PROM with Block Lock ™ Protection

IC MICROSYSTEMS 

X25170

Figure 5. Page Write Operation Sequence

CS

SCK

0 1 2 3 4 5 6 7 8 9 10

20 21 22 23 24 25 26 27 28 29 30 31

Instruction

SI

16 Bit Address

Data Byte 1

15 14 13

3210 76543210

CS

SCK

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Data Byte 2

Data Byte 3

SI

76543210 76543210

Data Byte N

6543210

Figure 6. Write Status Register Operation Sequence

CS

SCK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

SI

Data Byte

7 6 5 43 2 1 0

High Impedance

SO

Operational Notes

The X25170 powers-up in the following state:

– The device is in the low power standby state.

– A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

– SO pin is high impedance.

– The “write enable” latch is reset.

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

– The “write enable” latch is reset upon power-up.

– A WREN instruction must be issued to set the “write

enable” latch.

– CS must come HIGH at the proper clock count in order

to start a write cycle.

Characteristics subject to change without notice. 7 of 15

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