5962F-0422701QXA Просмотр технического описания (PDF) - Aeroflex Corporation
Номер в каталоге
Компоненты Описание
производитель
5962F-0422701QXA Datasheet PDF : 22 Pages
| |||
DQ0(0)
DQ1(0)
DQ2(0)
DQ3(0)
DQ4(0)
DQ5(0)
DQ6(0)
DQ7(0)
VSS
DQ0(1)
DQ1(1)
DQ2(1)
DQ3(1)
DQ4(1)
DQ5(1)
DQ6(1)
DQ7(1)
68 67 66 65 64 63 62 61 60 59 58 57 56 555453 52
1
51
2
50
3
49
4
48
5
6
Top View
47
46
7
45
8
44
9
43
10
42
11
41
12
40
13
39
14
38
15
37
16
36
17 1819 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
DQ0(2)
DQ1(2)
DQ2(2)
DQ3(2)
DQ4(2)
DQ5(2)
DQ6(2)
DQ7(2)
VSS
DQ0(3)
DQ1(3)
DQ2(3)
DQ3(3)
DQ4(3)
DQ5(3)
DQ6(3)
DQ7(3)
Figure 2. 17ns SRAM Pinout 68)
PIN NAMES
A(18:0) Address
DQ(7:0) Data Input/Output
En (4:1) Chip Enable
Wn (4:1) Write Enable
G
Output Enable
VDD1 Power (1.8V)
VDD2 Power (3.3V)
VSS Ground
DEVICE OPERATION
Each die in the UT8CR512K32 has three control inputs called
Chip Enable (En), Write Enable (Wn), and Output Enable (G);
19 address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). The chip enable (En) controls device selection, active,
and standby modes. Asserting En enables the device, causes IDD
to rise to its active value, and decodes the 19 address inputs to
each memory die by selecting the 2,048,000 byte of memory.
Wn controls read and write operations. During a read cycle, G
must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G
W
E I/O Mode Mode
X
X
1 3-state
Standby
X
0
0 Data in Write
1
1
0 3-state
Read2
0
1
0 Data out Read
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of Wn greater than VIH (min) with En and G less
than VIL (max) defines a read cycle. Read access time is
measured from the latter of Chip Enable, Output Enable, or valid
address to valid data output.
SRAM read Cycle 1, the Address Access, in Figure 3a, is
initiated by a change in address inputs while and chip is enabled
with G asserted and Wn deasserted. Valid data appears on data
outputs DQn(7:0) after the specified tAVQV is satisfied. Outputs
remain active throughout the entire cycle. As long as Chip
Enable and Output Enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (tAVAV).
SRAM read Cycle 2, the Chip Enable-controlled Access, in
Figure 3b, is initiated by En going active while G remains
asserted, Wn remains deasserted, and the addresses remain
stable for the entire cycle. After the specified tETQV is satisfied,
the eight-bit word addressed by A(18:0) is accessed and appears
at the data outputs DQn(7:0).
SRAM read Cycle 3, the Output Enable-controlled Access, in
Figure 3c, is initiated by G going active while En is asserted,
Wn is deasserted, and the addresses are stable. Read access time
is tGLQV unless tAVQV or tETQV have not been satisfied.
2
Share Link: 