5962F-0422701QXA Просмотр технического описания (PDF) - Aeroflex Corporation

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5962F-0422701QXA

UT8CR512K32 16 Megabit SRAM

Aeroflex Corporation 

Standard Products

UT8CR512K32 16 Megabit SRAM

Data Sheet

March 2009

www.aeroflex.com/Memories

FEATURES

‰ 17ns maximum access time

‰ Asynchronous operation for compatibility with industry-

standard 512K x 8 SRAMs

‰ CMOS compatible inputs and output levels, three-state

bidirectional data bus

- I/O Voltage 3.3 volts, 1.8 volt core

‰ Operational environment:

- Intrinsic total-dose: 300 krad(Si)

- SEL Immune >100 MeV-cm2/mg

- LETth (0.25): 53.0 MeV-cm2/mg

- Memory Cell Saturated Cross Section 1.67E-7cm2/bit

- Neutron Fluence: 3.0E14n/cm2

- Dose Rate

- Upset 1.0E9 rad(Si)/sec

- Latchup 1.0E11 rad(Si)/sec

‰ Packaging options:

- 68-lead ceramic quad flatpack (20.238 grams with lead

frame)

‰ Standard Microcircuit Drawing 5962-04227

- QML Q & V compliant part

INTRODUCTION

The UT8CR512K32 is a high-performance CMOS static RAM

multi-chip module (MCM), organized as four individual

524,288 words by 8 bit SRAMs with common output enable.

Easy memory expansion is provided by active LOW chip

enables (En), an active LOW output enable (G), and three-state

drivers. This device has a power-down feature that reduces

power consumption by more than 90% when deselected.

Writing to each memory is accomplished by taking the

corresponding chip enable (En) input LOW and write enable

(Wn) input LOW. Data on the I/O pins is then written into the

location specified on the address pins (A0 through A18). Reading

from the device is accomplished by taking the chip enable (En)

and output enable (G) LOW while forcing write enable (Wn)

HIGH. Under these conditions, the contents of the memory

location specified by the address pins will appear on the I/O pins.

The input/output pins are placed in a high impedance state when

the device is deselected (En HIGH), the outputs are disabled (G

HIGH), or during a write operation (En LOW and Wn LOW).

Perform 8, 16, 24 or 32 bit accesses by making Wn along with

En a common input to any combination of the discrete memory

die.

A(18:0)

G

W3

E3

W2

E2

W1

E1

W0

E0

512K x 8

512K x 8

512K x 8

512K x 8

DQ(31:24)

or

DQ3(7:0)

DQ(23:16)

or

DQ2(7:0)

DQ(15:8)

or

DQ1(7:0)

Figure 1. UT8CR512K32 SRAM Block Diagram

DQ(7:0)

or

DQ0(7:0)

1

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