UPD63310GK-9EU Просмотр технического описания (PDF) - NEC => Renesas Technology
Номер в каталоге
Компоненты Описание
производитель
UPD63310GK-9EU Datasheet PDF : 28 Pages
| |||
PIN FUNCTIONS
Pin Number
Pin Name
1
IN1R
2
IN2R
3
IN3R
4
IN4R
5
IN5
6
7
8
9
10-15
16
IN4L
IN3L
IN2L
IN1L
NC
MICOL
17
MICNL
18
MICPL
19
RBW
20
21, 22
23
OEB
NC
WB
24
RB
25
CSB
26
SELR
27, 28
TEST1, TEST2
29
RSTB
30
NC
µPD63310
(1/3)
I/O
Function
I
R-channel analog audio signal input pin 1
I
R-channel analog audio signal input pin 2
I
R-channel analog audio signal input pin 3
I
R-channel analog audio signal input pin 4
I
Analog audio signal (monaural) input pin. This channel accepts audio input
which is input to both left and right channels on the chip.
I
L-channel analog audio signal input pin 4
I
L-channel analog audio signal input pin 3
I
L-channel analog audio signal input pin 2
I
L-channel analog audio signal input pin 1
—
No connection
O
L-channel mic amp output pin. If the L-channel mic amp is not being used,
connect this pin to MICNL pin.
I
L-channel mic amp inverting input pin. If the L-channel mic amp is not being
used, connect this pin to MICOL pin.
I
L-channel mic amp noninverting input pin. If the L-channel mic amp is not
being used, connect this pin to VXLO pin.
O
Output pin for signal that specifies the bus driver’s direction. Output is at
high level when DATA5 to DATA0 are input pins and is at low level when
DATA5 to DATA0 are output pins. If not used, leave unconnected.
O
Bus driver enable signal output pin. When data input to DATA5 to DATA0
is enabled, output is at low level. If not used, leave unconnected.
—
No connection
I
Input pin for parallel interface’s data write signal. Used for input of low-level
signals when addresses are written to the volume setting register and when
data is written.
I
Input pin for parallel interface’s data read signal. Used for input of low-level
signals when data is read from the volume setting register.
I
Input pin for parallel interface’s chip select signal. Active low. When the
input signal is at high level, DATA5 to DATA0 are set for high impedance.
I
Input pin for signal that specifies the target register for parallel data input and
output. Specifies an address register when the input signal is at low level,
or a data register when the input signal is at high level.
I
Test mode setting pins. These pins set the test mode when at high level.
When not used (i.e., during normal operation mode), connect these pins to
GND.
I
Reset signal input pin. A reset occurs when a low pulse (pulse width of 1/
(8 fs) or greater) is input after starting MCLK. The case when a reset is
necessary is not only power-on but also an occurrence of disturbance in
master clock due to changing fS (sampling frequency). When input is at low
level, power down mode is set to reduce power consumption.
—
No connection
4
Share Link: 