UPD17P709GC-3B9 Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD17P709GC-3B9
NEC => Renesas Technology
UPD17P709GC-3B9 Datasheet PDF : 38 Pages
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µPD17P709
Pin No.
30
79
Symbol
VDD1
VDD0
31
VCOH
32
VCOL
Function
Power supply. Apply the same voltage to the VDD1 and VDD0 pins.
• When the CPU and peripheral functions are operating: 4.5 to 5.5 V
• When only the CPU is operating: 3.5 to 5.5 V
• When the clock is stopped: 2.2 to 5.5 V
Input for PLL local oscillation (VCO) frequency
• VCOH
• Active when VHF mode is selected by software. Otherwise, pulled
down.
• VCOL
• Active when HF or MW mode is selected by software. Otherwise,
pulled down.
Output format
—
—
34
EO0
35
EO1
Inputs to these pins are to be AC-amplified. Cut, therefore, the DC
components in the input signals by using capacitors.
Output from the charge pump of the PLL frequency synthesizer. The
result of phase comparison between the divided local oscillation fre-
quency and reference frequency is output.
CMOS tristate
Power-on reset
When reset
WDT&SP reset
CE reset
When the clock
is stopped
High-impedance High-impedance High-impedance High-impedance
output
output
output
output
36
TEST
Test input pin.
—
Be sure to connect it to GND.
37
P1D3
38
P1D2
Output for port 1D and BEEP
• P1D3-P1D0
39
P1D1/BEEP1
• 4-bit I/O port
40
P1D0/BEEP0
• Input/output can be specified bit by bit.
• BEEP1, BEEP0
• BEEP output
CMOS push-pull
Power-on reset
Input
(P1D3-P1D0)
When reset
WDT&SP reset
CE reset
Input
(P1D3-P1D0)
Held
(P1D3-P1D0)
When the clock
is stopped
Held
(P1D3-P1D0)
43
P2B3
to
to
46
P2B0
4-bit I/O port.
Input/output can be specified bit by bit.
Power-on reset
Input
When reset
WDT&SP reset
Input
CE reset
Held
When the clock
is stopped
Held
CMOS push-pull
47
P3C3
to
to
50
P3C0
4-bit I/O port.
Input/output can be specified in 4-bit units.
Power-on reset
Input
When reset
WDT&SP reset
Input
CE reset
Held
When the clock
is stopped
Held
CMOS push-pull
11
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