TSC87C52-25CHB Просмотр технического описания (PDF) - Temic Semiconductors

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TSC87C52-25CHB

CMOS 0 to 33 MHz Programmable 8–bit Microcontroller

Temic Semiconductors 

TSC87C52

Symbol

REN

TB8

RB8

TI

RI

Description

Serial Reception Enable bit

Set to enable serial reception.

Clear to disable serial reception.

Ninth bit to transmit in mode 2 and 3

Set to transmit a logic 1 in the 9th bit.

Clear to transmit a logic 0 in the 9th bit.

Ninth bit received in mode 2 and 3

Set by hardware if 9th bit received is logic 1.

Clear by hardware if 9th bit received is logic 0.

Transmit Interrupt Flag

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other

modes.

Clear to acknowledge interrupt.

Receive Interrupt Flag

Set by hardware at the end of the 8th bit time in mode 0, see Figure 4 and Figure 5 in the other modes.

Clear to acknowledge interrupt.

The reset value of SCON is 0000 0000b.

Timer 2

The Timer 2 in the TSC87C52 operates identically to the Timer 2 in the 80C52 but includes the following

enhancements. For a complete understanding of the TSC87C52 Timer 2 please refer to the description in the 80C51

Hardware Description Guide.

Auto–reload (up or down counter)

Enhanced Timer 2 can now be programmed to count up or down when configured in its 16–bit auto–reload mode. This

feature is controlled by the DCEN (Down Counter Enable) bit. DCEN is located in T2MOD at bit location 0 (see

Table 5). Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 6. In this mode the T2EX pin

controls the direction of count.

A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at FFFFh and set the TF2 bit. This overflow also

causes the 16–bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. Now the timer underflows when TH2 and TL2 equal the values stored

in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes FFFFh to be reloaded into the timer registers.

The EXF2 bit toggles whenever Timer 2 overflows or underflows. In this operating mode, EXF2 does not flag an

interrupt.

(DOWN COUNTING RELOAD VALUE)

FFh

FFh

(8–bit) (8–bit)

OSC

÷ 12

T2

C/T2

TR2

TL2 TH2

(8–bit) (8–bit)

TOGGLE

EXF2

TF2

TIMER 2

INTERRUPT

RCAP2L RCAP2H

(8–bit) (8–bit)

(UP COUNTING RELOAD VALUE)

COUNT DIRECTION

1= UP

0= DOWN

T2EX

Figure 6 Timer 2 Auto–Reload Mode Up/Down Counter

MATRA MHS

9

Rev. C – 10 Sept 1997

Preliminary

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