Table 3. Electrical Specifications (Continued)
Parameter
Test
Value
Symbol Level
Min
Typ
Max
Gain error drift
Offset error drift
–
4
100
125
150
–
4
40
50
60
Transient Performance
Bit error rate
FS = 500 Msps, FIN = 62.5 MHz
ADC settling time
VIN -VINB = 400 mVpp
Overvoltage recovery time
BER
4
–
–
1E-13
TS
4
–
0.5
1
TOR
4
–
0.5
1
AC Performance
Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), binary output data format,
Tj = 70°C, unless otherwise specified
Signal to noise and distortion ratio
SINAD
–
–
–
–
FS = 500 Msps, FIN = 20 MHz
FS = 500 Msps, FIN = 500 MHz
FS = 500 Msps, FIN = 1000 MHz (-1 dBFS)
FS = 50 Msps, FIN = 25 MHz
Effective number of bits
–
4
43
45
–
–
4
42
44
–
–
4
38
40
–
–
1
43
46
–
ENOB
–
–
–
–
FS = 500 Msps, FIN = 20 MHz
FS = 500 Msps, FIN = 500 MHz
FS = 500 Msps, FIN = 1000 MHz (-1 dBFS)
FS = 50 Msps, FIN = 25 MHz
Signal to noise ratio
–
4
7.0
7.2
–
–
4
6.8
7.0
–
–
4
6.0
6.3
–
–
1
7.0
7.4
–
SNR
–
–
–
–
FS = 500 Msps, FIN = 20 MHz
FS = 500 Msps, FIN = 500 MHz
FS = 500 Msps, FIN = 1000 MHz (-1 dBFS)
FS = 50 Msps, FIN = 25 MHz
Total harmonic distortion
–
4
44
46
–
–
4
44
45
–
–
4
40
43
–
–
1
44
45
–
|THD|
–
–
–
–
FS = 500 Msps, FIN = 20 MHz
–
4
50
53
–
Unit
ppm/°C
ppm/°C
Error/
sample
ns
ns
–
dB
dB
dB
dB
–
Bits
Bits
Bits
Bits
–
dB
dB
dB
dB
–
dB
Note
(2)(4)
(2)
(2)
(2)
(2)
(2)
FS = 500 Msps, FIN = 500 MHz
FS = 500 Msps, FIN = 1000 MHz (-1 dBFS)
FS = 50 Msps, FIN = 25 MHz
–
4
48
50
–
dB
–
4
38
40
–
dB
–
1
44
54
–
dB
6 TS8308500
2193A–BDC–04/03