TS8308500 Просмотр технического описания (PDF) - Atmel Corporation
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TS8308500 Datasheet PDF : 50 Pages
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TS8308500
Table 3. Electrical Specifications (Continued)
Parameter
Test
Value
Symbol Level
Min
Typ
Max
Unit
Clock input power level
–
4
-2
4
10
dBm
Clock input capacitance
CCLK
4
–
3
3.5
pF
Digital Outputs
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), binary output data format,
Tj (typical) = 70°C. Full temperature range: 0°C < Tc; Tj < +90°C or -40°C < Tc ; Tj < 110°C
Logic compatibility for digital outputs
(Depending on the value of VPLUSD) (14)
Differential output voltage swings
(assuming VPLUSD = 0V):
75Ω open transmission lines (ECL levels)
–
–
ECL or LVDS
–
–
4
–
–
–
–
–
–
1.5
1.620
–
V
75Ω differentially terminated
–
–
0.70
0.825
–
V
50Ω differentially terminated
–
–
0.54
0.660
–
V
Output levels (assuming VPLUSD = 0V)
75Ω open transmission lines:
–
4
–
–
–
–
Logic 0 voltage
Logic 1 voltage
Output levels (assuming VPLUSD = 0V)
75Ω differentially terminated:
VOL
–
–
-1.62
-1.54
V
VOH
–
-0.88
-0.8
–
V
–
4
–
–
–
–
Logic 0 voltage
Logic 1 voltage
Output levels (assuming VPLUSD = 0V)
50Ω differentially terminated:
VOL
–
–
-1.41
-1.34
V
VOH
–
-1.07
-1
–
V
–
–
–
–
–
–
Logic 0 voltage
Logic 1 voltage
Differential Output Swing
VOL
1, 2
–
-1.40
-1.32
V
VOH
1, 2
-1.16
-1.10
–
V
DOS
4
270
300
–
mV
Output level drift with temperature
–
4
–
–
1.6
mV/°C
DC Accuracy
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
Tj (typical) = 70°C
Differential non linearity
DNL-
1
-0.6
-0.4
–
lsb/V
Differential non linearity
DNL+
1
–
0.4
0.6
lsb/V
Integral non linearity
INL-
1
-1.2
-0.7
–
lsb/V
Integral non linearity
INL+
1
–
0.7
1.2
lsb/V
No missing codes
–
Guaranteed over specified temperature range
Gain
–
1, 2
90
98
110
%/V
Input offset voltage
–
1, 2
-26
-5
26
mV/V
Note
(1)(6)
(6)
(6)
(6)
(2)(3)
(2)(3)
(3)
5
2193A–BDC–04/03
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