TRC101 Просмотр технического описания (PDF) - RF Monolithics, Inc

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TRC101

300-1000 MHz RF Transceiver

RF Monolithics, Inc 

The receive data rate is programmable from 337bps to 344kbps. An internal prescaler is used to give

better resolution when setting up the receive data rate. The prescaler is optional and may be disabled

through the Data Rate Setup Register.

The type of baseband filtering is selectable between an Analog filter and a Digital filter. The analog filter

is a simple RC lowpass filter. An external capacitor may be chosen depending on the actual data rate.

The chip has an integrated 10K Ohm resistor in series that makes the RC lowpass network. With the

analog filter selected, a maximum data rate of 256kbps can be achieved. The digital filter is used with a

clock frequency of 29X data rate. In this mode a clock recovery (CR) circuit is used to provide for a

synchronized clock source to recover the data using an external processor. The CR has three modes of

operation: fast, slow, and automatic, all configurable through the Baseband Filter Register. The CR

circuit works by sampling the preamble on the incoming data. The preamble must contain a series of 1’s

and 0’s in order for the CR circuit to properly extract the data timing. In slow mode the CR circuit requires

more sampling (12 to 16 bits) and thus has a longer settling time before locking. In fast mode the CR

circuit takes fewer samples (6 to 8 bits) before locking so settling time is not as long and timing accuracy

is not critical. In automatic mode the CR circuit begins in fast mode to coarsely acquire the timing period

with fewer samples and then changes to slow mode after locking. Further details of the CR and data rate

clock are provided in the Baseband Filter Register. CR is only used with the digital filter and data rate

clock. These are not used when configured for the analog filter.

Transmit Register

The transmit register is configured as two 8-bit shift registers connected in series to form a single 16-bit

shift register. On POR the registers are filled with the value AAh. This can be used to generate a

preamble before sending actual data. When the transmitter is enabled through the Power Management

Register, transmission begins immediately and the value in the transmit register begins to be sent out. If

there is nothing written to the register then it will send out the default value AAh. The next data byte can

be loaded via the SPI bus to the transmit register by monitoring the SDO pin for a logic ‘1’ or waiting for

an interrupt from the nIRQ pin. After data has been loaded to the transmit register the processor must

wait for the next interrupt before disabling the transmitter or the rest of the data left in the register will be

lost. Inserting a dummy byte of all 0’s is recommended for the last byte of data loaded.

Receive FIFO

The receive FIFO is configured as one 16-bit register. The FIFO can be configured to generate an

interrupt after a predefined number of bits have been received. This threshold is programmable from 1 to

15 bits. It is recommended to set the threshold to at least half the length of the register (8 bits) to insure

the external host processor has time to set up.

The receive FIFO may also be configured to fill only when valid data has been identified. The TRC101

has a synchronous pattern detector that watches incoming data for a particular pattern. When it sees this

pattern it begins to store any data that follows. At the same time, if pin 16 is configured for Valid Data

Detector output (See Receiver Control Register), this pin will go ‘high’ signaling valid data. This can be

used to prepare a host processor for retrieving data. The internal synchronous pattern is set to 2DD4h

and is not configurable.

The FIFO can be read out through the SDO pin only by toggling the nFSEL pin (6) which selects the FIFO

for read and reading out data on the next clock. The FINT pin (7) will stay active (logic ‘1’) until the last bit

has been read out, and it will then go ‘low’. This pin may also be polled to watch for valid data. When the

number of bits received in the FIFO match the pre-programmed limit, this pin will go active (logic ‘1’) and

stay active until the last bit is read out as above. An alternative method of reading the FIFO is through an

SPI bus Status Register read. The drawback to this is that all interrupt and status bits must be read first

before the FIFO bits appear on the bus. This could pose a problem for receiving large amounts of data.

The best method is using the SDO pin and the associated FIFO function pins.

Automatic Frequency Adjustment (AFA)

The PLL has the capability to do fine adjustment of the carrier frequency automatically. In this way, the

receiver can minimize the offset between transmit and receive frequency. This function may be enabled

or disabled through the Automatic Frequency Adjustment Register. The range of offset can be

programmed as well as the offset value calculated and added to the frequency control word within the

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