TC3097-8 Просмотр технического описания (PDF) - Unspecified
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TC3097-8 Datasheet PDF : 35 Pages
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Pin No.
Symbol
LED Driver Pins
6-13
LRLED2 to
LRLED9
5
LRLED1
91-99
PALED1 to
PALED9
TC3097-8
Preliminary Data Sheet
I/O
Description
O Link/Receive LED (active-Low):
This CMOS output goes active when the link integrity test is pass
on LEMRIC's TP port network segment and blinks when this
device is receiving from its link passing TP port segment.
O AUI Receive LED (Active-Low):
This CMOS output is powered on active and blinking when this
device is receiving from its AUI port network segment.
O Port Partition Jabber LED (Active-Low):
This CMOS output goes active when the LEMRIC's network
connection port is partitioned from its network segment and then
goes inactive when its network connection port is reconnection
from its network segment.
Pin No.
Symbol
TEST Support Pins
28
TEST1
29
TEST3
30
TEST4
I/O
Description
B These pins are used to facilitate device testing. When not in test
mode, these pins should be left open. [Note:] Pins TEST3 and
TEST4 can be used to modify the build in 10BASE-T operation.
TEST1 can be used to configure LED display mode (ICPLUS or
AMD compatible mode). Refer to port Block Function section for
more details.
Pin No.
Symbol
RESET & CLOCK Pins
23
RESETZ
25
CLK1
26
CLK2
I/O
Description
I Optional device Reset. A low on this pin causes the device to
reset. RESET must be high for normal operation, when not used,
please leave open.
I System Clock. 20 MHz, 50% nominal, 40/60% worst case, duty
O cycle. The worst-case frequency tolerance and duty cycle limit the
range over which the LEMRIC will operate correctly. However,
since this clock is used for Manchester data transmission, jitter
performance will degrade if clock sources with relatively large
tolerances are used.
Pin No.
Symbol
Decoder Filer Pins
33
CP1_O
32
VCO_I
I/O
Description
I Phase Lock Loop delay line external filter. This pin should be
connected correctly with a capacitor to AVDD or causing the
analog PLL of the device to be failed.
I Phase Lock Loop VCO external filter. This pin should be
connected correctly with a RC filter circuit to AVDD or causing the
analog PLL of the device to be failed.
Confidential.
6/35
Copyright © 2003, IC Plus Corp.
July 21. 2003
TC3097-8-DS-R24
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