ST16C1450
2.97V TO 5.5V UART
xr
REV. 4.2.1
3.0 UART INTERNAL REGISTERS
The 1450 has a set of configuration registers selected by address lines A0, A1 and A2. The 16C450
compatible registers can be accessed when LCR[7] = 0 and the baud rate generator divisor registers can be
accessed when LCR[7] = 1. The complete register set is shown on Table 2 and Table 3.
TABLE 2: ST16C1450 UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES
REGISTER
READ/WRITE
0 00
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
0 00
DLL - Div Latch Low Byte
Read/Write
0 01
DLM - Div Latch High Byte
Read/Write
0 01
IER - Interrupt Enable Register
Read/Write
0 10
ISR - Interrupt Status Register
Reserved
Read-only
Write-only
0 11
LCR - Line Control Register
Read/Write
1 00
MCR - Modem Control Register
Read/Write
1 01
LSR - Line Status Register
Reserved
Read-only
Write-only
1 10
MSR - Modem Status Register
Reserved
Read-only
Write-only
1 11
SPR - Scratch Pad Register
Read/Write
COMMENTS
LCR[7] = 0
LCR[7] = 1
LCR[7] = 0
LCR[7] = 0
10