ST10F163
XVI.4.7 Phase locked loop ......................................................................................................
35
XVI.4.8 Memory cycle variables ..............................................................................................
36
XVI.4.9 External clock drive XTAL1 .......................................... .............................................. 37
XVI.4.10 Multiplexed bus ...................................................................................... .................... 38
XVI.4.11 Demultiplexed bus ......................................................................................................
44
XVI.4.12 CLKOUT and READY ................................................................................................
50
XVI.4.13 External bus arbitration ........................................................................... .................... 52
XVI.4.14 Synchronous serial port timing ...................................................................................
54
XVII
PACKAGE MECHANICAL DATA ...........................................................................
56
XVIII
ORDERING INFORMATION ......................................................................................
56
XIX
REVISION HISTORY ................................ ................................................................. 57
3/58