SPT5126BCQ Просмотр технического описания (PDF) - Signal Processing Technologies

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SPT5126BCQ

16-BIT ULTRAHIGH SPEED DAC

Signal Processing Technologies 

TERMINOLOGY

INTEGRAL LINEARITY ERROR

Integral linearity error is a measure of the maximum deviation

from a straight line passing through the end points of the DAC

transfer function. It is measured after adjusting for zero offset

error and zero gain error.

DIFFERENTIAL LINEARITY ERROR

Differential linearity error is the difference between the mea-

sured change and the ideal 1 LSB change between two

adjacent codes. A specified differential nonlinearity of <1 LSB

ensures monotonicity and no missing codes.

OFFSET ERROR AND GAIN ERROR

Offset error is the absolute difference between actual and

theoretical output voltage at code all 1s.

Gain error is the difference between the measured and ideal

full scale output range (after offset has been adjusted to zero)

expressed as a percent of the ideal output level. The actual

full scale output contains both the gain error and the offset

error. Both offset and gain errors are adjustable to zero using

the external trim network shown in figures 4 and 5 respec-

tively.

OUTPUT COMPLIANCE

Output compliance is the allowable range of voltage swing for

pin DAC OUT. Other specifications, such as integral

nonlinearity, are not guaranteed beyond the specified output

compliance voltage.

sively divides the (remaining) reference current to produce a

binary weighted current division. In other words, in moving

down the ladder, each 2R resistor leg has half the current flow

of the previous leg. Each 2R resistor leg is connected to a

current source that is trimmed during manufacturing to pro-

vide the 16-bit accuracy. Bipolar switches within each leg are

controlled by the respective data bits (pins D0 through D15).

When the controlling data bit is low, the 2R resistor leg current

is steered to pin DAC OUT. When the data bit is high, the leg

current is steered to the DAC RTN pins (DAC RTN 1, and

DAC RTN 2), which are externally connected to analog

ground.

Figure 1 illustrates the equivalent output circuit of the SPT5216

showing on-chip application resistors and parasitic capaci-

tances.

Figure 1 - Equivalent SPT5216 Output Circuit

DAC

0-5 mA

1 kΩ

1 kΩ

8 pF

Substrate

8 pF

Substrate

1 kΩ

12 pF

5Ω

Substrate

VEE

APPLICATION INFORMATION

10 V FSR

5 V FSR

DAC Out

DAC RTN

Sense

DAC RTN 1

DAC RTN 2

AGND

GENERAL CIRCUIT DESCRIPTION

ACTIVE CURRENT-TO-VOLTAGE CONVERSION

The SPT5216 uses a unique design approach to set a new

standard in monolithic DAC performance. It delivers excep-

tional 16-bit accuracy and stability over temperature and, at

the same time, exhibits an extremely fast 150 ns settling time.

On chip support functions include a stable band-gap voltage

reference and application resistors for output scaling. Inclu-

sion of these functions reduces the external analog compo-

nent requirements and further increases accuracy. Digital

circuitry on the chip is kept to a minimum (limited to the digital

inputs), thus minimizing internal noise generation and provid-

ing interface flexibility.

DAC CIRCUITRY

The SPT5216 uses current source segmentation for the most

significant bits and an R-2R ladder for the least significant

bits. The ladder, which consists of a resistor network, succes-

In many DAC applications the output current needs to be

converted into a usable voltage signal. The most common

current-to-voltage configuration for the SPT5216 output is

shown in figure 2. Here, an external op amp in conjunction

with the internal feedback resistor(s) are used for current-to-

voltage (I-to-V) conversion. The op amp provides both a

buffered VOUT and maintains DAC OUT at a virtual ground.

This way, VOUT can provide up to a 10 volt output swing

(using internal feedback resistors) and the output compliance

specification (±2.5 volts maximum) is met.

VOUT swing is determined by the feedback resistance. For a

5 volt VOUT swing, the op amp's output is connected to

pin 5 V FSR (Full Scale Range) which provides an internal

1 kΩ feedback resistance. A 10 volt VOUT swing is derived by

connecting the op amp output to pin 10 V FSR. This feedback

connection option is illustrated by the dotted line in figure 2.

SPT

4

SPT5216

3/4/97

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