VP2611CGGH1R Просмотр технического описания (PDF) - Mitel Networks

Номер в каталоге

Компоненты Описание

производитель

VP2611CGGH1R

H.261 Encoder

Mitel Networks 

VP2611

low. Note that in the data read phase CADR must always go

high before CSTR goes high, with the set up time specified.

When CEN goes high, or CADR goes low, the CBUS will go

high impedance after the delay specified.

Note that the access times under the conditions given

above are only true when the gap between CSTR going high

in the instruction phase, and CEN going low in the data phase,

is greater than the minimum specified in figure 10.

Only the four LSBs, CBUS3:0, are used when writing

instructions to the VP2611. The remaining bits, CBUS7:4,

should be pulled low while the instruction is strobed into the

VP2611.

The instructions listed in Table 3 are described below in

greater detail;

Input VAR Threshold: VAR is the difference between the best

fit MAE value and the variance of the current macroblock.

The VAR Threshold is the best fit MAE value below which

Inter Frame Prediction is always used, no matter what the

variance of the current block. Above this threshold inter

mode coding is only used if the best fit value is less than

the current block variance. The default value is 3, within a

range of 0 - 255 using the eight most significant bits of the

14 bit value. In normal operation values below 15 should

be used.

Input Inter Quantiser: Coefficents of inter coded macroblocks

will be quantized using the value on CBUS4:0 following

this instruction. Internally this represents a 6 bit number

with the lsb always zero, giving a value between 0 and 62

in steps of two. Where only one quantization value is to be

used for both inter and intra cases, this instruction should

be used. On reset the value will default to the maximum

allowed. See note below.

Input Intra Quantiser: This instruction is similar to the above,

except that it defines the quantization level for intra mode

coding when it is to be different to that of inter mode coding.

See note below.

Input Setup Data: This instruction allows several user defined

options to be specified, using individual bits in the following

data word. If CBUS0 is LOW the device will work in full CIF

mode , if HIGH it uses the QCIF mode. If CBUS3 is HIGH

both inter and intra quantization values will be used,

otherwise a common value will be used. If CBUS5 is high

then the motion compensation circuits will be disabled. If

CBUS6 is high, then the device will be configured to use

256K x 16 or 256K x 4 DRAM's, otherwise it will assume the

use of two 64K x 16 DRAM's. The default conditions after

RESET are those selected by the Low level. CBUS1,

CBUS2, CBUS4 and CBUS7 are not used but must be low

during the definition phase. This instruction may be used

any time after RESET has gone high, but the video input

bus must not be active. If a subsequent mode change

between CIF and QCIF is made then a further RESET is

needed.

Input Control Functions: This instruction specifies several

control options using individual bits in the following data

word. If CBUS0 is HIGH then the on board Inter/Intra

Decision circuitry will be overidden according to CBUS1;

if CBUS1 is HIGH then all subsequent macroblocks will be

intra coded, if it is LOW they will be inter coded. When

CBUS2 is HIGH the on-board Filter Decision circuitry is

overidden according to CBUS3; if CBUS3 is HIGH then the

filter will be forced on, if it is LOW the filter will be forced off.

If CBUS4 is HIGH then FIX MB will be implemented, and

no new data from the current macroblock will be coded. A

two macroblock delay exists between defining the Force

Inter/Intra, Force Filter or FIX MB decisions through the

control bus and data being affected at the outputs. These

decisions will stand for all subsequent macroblocks until

they are again changed. If CBUS5 is HIGH a FAST

UPDATE will be performed on the next frame and all

blocks will be coded in intra mode. If CBUS6 is HIGH then

the next frame will not be transmitted ( SKIP FRAME ).

Note that these two global frame bits do not take effect until

the start of the next frame, and stay in effect for all frames

until they are removed. If CBUS7 is HIGH, then the on-

board Force Update Controller will be overidden, and the

user will have to enforce their own Force Update policy

using the Force Intra command. RESET will cause the

options to default to those defined by the LOW state. Note

that SKIP FRAME has priority over any other bits and that

FIXMB has priority over all bits bar SKIP FRAME. See

note below.

Output GOB Number: This instruction will output the GOB

Number on CBUS3:0, for the data currently being output

on DBUS. CBUS7:4 are not used (always low).

Output MB Number: This instruction will output the macrob-

lock number on CBUS5:0, for the data currently being

output on DBUS. If CBUS6 is low it indicates that the

macroblock number has just changed, or is about to

change. New Quantization Value or Control Function

words should not be written at this time since it is uncertain

which macroblock they will effect. CBUS7 is not used

(always low).

Output Control Decisions: This instruction will output the

details of several control decisions on the CBUS. CBUS0

shows whether the MacroBlock currently being output on

DBUS was inter or intra coded (0=Intra). CBUS1 shows

whether motion compensation was used (1=MC used).

CBUS3 shows whether the macroblock was passed

through the loop filter or not (1=Filtered). CBUS4 will be

high if the FIX MB instruction was enforced. CBUS5 will be

high if FAST UPDATE is currently being undertaken.

CBUS6 will be high if SKIP FRAME is in force. CBUS2 and

CBUS7 are not used.

Output Setup Data: This instruction allows the user to verify

the internal setup previously selected. The bits have the

same significance as in the Input Setup Data Instruction.

Note

For definitive operation the output MB number should be

read first, and these bytes only changed if CBUS b is high.

9

Share Link: