VP2611CGGH1R Просмотр технического описания (PDF) - Mitel Networks

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производитель

VP2611CGGH1R

H.261 Encoder

Mitel Networks 

VP2611

SCLK

DCLK

20ns max

25ns max

DATA FROM

VP2611

20ns max

DATA VALID

DMODE

3:0

DATA VALID

Fig 8: Timing diagram

GOB Number : At the start of each new macroblock, the

current GOB Number is output on DBUS3:0. (DBUS3 is

MSB).

MB Number : After the GOB Number, the macroblock

Number is output on DBUS5:0 (DBUS5 is MSB).

Coded Block Pattern : This byte contains a 6 bit linear code

that indicates which of the sub-blocks actually contain

coded data. DBUS6 will be high if sub-block 1 contains

coded data, through to DBUS 1 being high if sub-block 6

contains coded data. DBUS7 and DBUS0 are not used.

Note that if the macro block is not motion compensated

and the coded block pattern is all zero's, the fixed macro

block bit will be set in the control decisions byte.

Quant Value :The quantisation value used in processing the

current macroblock is output on DBUS4:0 (DBUS4 is

MSB). This represents an actual quantisation level be-

tween 2 and 62, in steps of 2 and as defined in H.261.

Horizontal MV : If motion compensation is used, the horizontal

component of the motion vector will be output on DBUS4:0

(DBUS4 is MSB). This 5 bit value represents a two's

complement number in the range +/-15

(although only vectors in the range -8 to +7 are currently

possible with the VP2611).

Vertical MV : If motion compensation is used, the vertical

component of the motion vector will be output on DBUS4:0

(DBUS4 is MSB). This 5 bit value represents a two's

complement number in the range ±15 ( although only

vectors in the range ±7 are currently possible with the

VP2611).

CBUS3:0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

INSTRUCTION

Input VAR Threshold

Reserved

Input Inter Quantiser

Input Intra Quantiser

Input Setup Data

Input Control Functions

Reserved

Reserved

Output GOB Number

Output MB Number

Reserved

Output Control Decisions

Output Setup Data

Reserved

Reserved

Overide internal clock doubler

Table 3 : CBUS Instruction Codes

Sub-block Number : An identifier for the run length coded

coefficients which are about to be made available. DBUS

2:0 contain the coded sub-block number from 1 to 6. All

zero sub-blocks will not be produced at the outputs, and

their corresponding numbers will not appear.

Zero Run Count : The number of zero valued coefficents

preceding the next non zero coefficient is available on

DBUS5:0 (DBUS5 is MSB). Normally, DBUS7:6 are low,

except to signify the end of a Sub-block, when they will

both be high. Zero Run Count is always followed by a

coefficient, even at the end of a sub-block.

RLC Coefficient : This byte contains the 8 bit coefficient value.

It will always be a non-zero value, except when the

previous Zero Run Count signalled the end of sub-Block.

A zero value is then possible since, as stated above, the

run count is always followed by a coefficient byte, which

may be zero if the last coefficient is zero.

Wait State : This indicates that no valid data is being output

from the DBUS port during this cycle. No DCLK is pro-

duced for this state.

Pins which are "not used" for certain functions will be

forced low.

This diagram shows a typical Sub-block being output from the VP2611.

DCLK

DMODE

15 7

8 9 15 8 9 15 8 9 15

DBUS

X2

0

4 X 1 -2 X 252 0 X

Both msb's are high showing end of block.

Fig 9: DBUS Timing

7

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