VP2611CGGH1R Просмотр технического описания (PDF) - Mitel Networks

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VP2611CGGH1R

H.261 Encoder

Mitel Networks 

VP2611

DBUS Output Port

The DBUS port is used to pass data and control informa-

tion directly to the VP2612 Video Multiplexer. The type of data

on the output pins is identified by the DMODE 3:0 outputs,

using the codes shown in Table 2. An output strobe is also

produced ( DCLK ) which always goes high one system clock

period after the data defined by DMODE 3:0 becomes valid.

This edge is used to strobe the data into the Video Multiplexer,

and thus the data set up time is always one SYSCLK period

minus differential output delays.

The number of SYSCLK periods during which data re-

mains valid is dependent on the type of data, and DCLK

remains high for this same period. It goes low as the result of

the same SYSCLK rising edge which produces a change in

DMODE 3:0. The output delays with respect to SYSCLK are

illustrated in Figure 8, and Figure 9 shows a typical output

sequence during which DCLK remains high for several cycles

as the sub-block number ( code 7 ) is produced. During a Wait

State

( code 15 ) no DCLK transitions are produced. The actual

sequence of output events which occur for each macroblock,

and the duration of each event, are illustrated in Figure 7.

The output events are defined in more detail below;

Control Decisions : This byte shows which control decisions

have been taken for the forthcoming macroblock. DBUS0

will be high if a Fixed Macroblock (FIX MB) was enforced

i.e. no new data will be transmitted this macroblock.

DBUS1 indicates whether Inter (high) or Intra (low) coding

was used for the macroblock. DBUS2 will be high if the

macroblock was filtered, and DBUS3 will be high if motion

compensation was used. DBUS5 will be high if the current

frame is being coded in FAST UPDATE mode. In this

mode the complete frame will be intra coded. DBUS6 will

be high if the current frame is a SKIP FRAME i.e. not being

coded - so no coefficients will be transmitted. DBUS4 and

DBUS7 are not used.

DMODE3:0

FUNCTION

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

GOB Number

MB Number

Control Decisions

Quant Value

Horizontal MV

Vertical MV

Coded Blk Pattern

Sub-Block No

Zero Run Count

RLC Coefficient

Not used

Not used

Not used

Not used

Not used

Wait State

Table 2 : DBUS Functions

6

START MB

WAIT

(2 cycles)

IS IT

A DUMMY

BLOCK?

no

CONTROL

yes

(2 cycles)

GOB

(2 cycles)

MB

CBP

(2 cycles)

(2 cycles)

QUANT

(2 cycles)

HORZ MV (2 cycles)

VERT MV (2 cycles)

ARE

no

ANY BLOCKS

CODED?

yes

WAIT

(32 cycles)

SUB BLK NO (15 cycles)

RUN LENGTH (2 cycles)

MAGNITUDE (2 cycles)

WAIT

(1 cycle)

ARE

ALL COEFFS

no O/P?

yes

WAIT

(wait variable time to make total

time since start of sub-block up

to 335 cycles)

no

ARE

ALL BLOCKS

O/P?

yes

WAIT

(variable cycles)

END MB

Fig 7 : DBUS Port Flow Chart

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