VP2611CGGH1R Просмотр технического описания (PDF) - Mitel Networks

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производитель

VP2611CGGH1R

H.261 Encoder

Mitel Networks 

VP2611

2064 cycles

YUV Input

MB1

MB2

MB3

MB4

Frame Store Read

DUMMY

MB1

MB2

MB3

Control Decisions

DUMMY

MB1

MB2

MB3

Frame Store Write

DUMMY

DUMMY

DUMMY

MB1

DBUS Output

DUMMY

DUMMY

DUMMY

MB1

Fig 4: MacroBlock Pipelining

SUBBLOCK ORDER WITHIN MACROBLOCK

1

2

5

6

3

4

U

V

Y

OPERATION OF INTERFACES

PIXEL ORDER WITHIN SUBBLOCK

Macroblock Delays

The VP2611 has a three macroblock pipeline delay be-

tween pixel inputs and run length coded outputs. This is

illustrated in Figure 4. Whilst the second macroblock is being

input, the best fit macroblock from the previous frame is being

identified and then read from the frame store. At this time any

Control Decisions which are to effect the first macroblock must

be supplied by the host controller. The run length coded

outputs for the first macroblock are not available until the

fourth macroblock is supplied at the input pins.

YUV Input Port

The YUV port accepts pixel data from the preprocessor in

block format as illustrated in Figure 5. Within a complete

system the VP2611 is always the master device, and must be

supplied with macroblock data when it makes a demand. The

order in which pixels are supplied is pre-determined, and must

be strictly maintained. There are 64 pixels per sub-block and

4 luminance and 2 chrominance sub-blocks per macroblock.

The macroblocks themselves are divided into groups of blocks

( GOB's ), and the sequence specified in H.261 must also be

maintained. Note that, since the chrominance resolution is half

the luminance resolution both vertically and horizontally, then

the two chrominance blocks cover the same picture area as

the four luminance blocks.

The pre-processor producing macroblock data must pro-

duce a frame start signal ( FRMIN ) when it has a complete

frame of data available. This resets the input controller within

the VP2611, which will then generate sequential GOB and

macroblock numbers for the coded outputs referenced to this

input.

FRMIN must go high for at least one system clock period,

and must go low before the next frame is available. The

VP2611 responds to FRMIN with a request for macroblock

data ( REQYUV ), which occurs approximately 184 SYSCLK

periods after FRMIN. It must then receive a complete macrob-

lock within 1871 SYSCLK periods, and at the end of this time

REQYUV will go inactive. The VP2611 must be provided with

a PCLK signal to strobe in the data. This must be derived from

SYSCLK, and must only be present when there is valid data

at the input. Data must meet the set up and hold times with

respect to PCLK as specified in Figure 6.

The maximum peak rate for PCLK is the SYSCLK rate

divided by two, but since there are 384 bytes per macroblock

00 01 02 03 04 05 06 07

08 09 10 11 12 13 14 15

16 17 18 0139 20 21 22 23

24 25 26 27 28 29 30 31

32 33 34 35 36 37 38 39

40 41 42 43 44 45 46 47

48 49 50 51 52 53 54 55

56 57 58 59 60 61 62 63

Fig 5 : Ordering of Pixels

then theoretically the average rate need only be 384/1871

times the SYSCLK rate. Note that PCLK must always be

obtained by dividing SYSCLK by an integer greater than one.

When the VP520 CIF/QCIF Converter is supplying the VP2611

with data, it provides a peak PCLK rate equivalent to SYSCLK

divided by two, and an average rate of SYSCLK divided by

four.

The mimimum gap between REQYUV going active is

2064 SYSCLK periods. In full CIF mode "dummy" macrob-

locks are internally inserted between rows, in order to give the

chip sufficient time to load a new search window. No new YUV

data must be loaded during these dummy macroblocks, and

REQYUV will remain inactive. No dummy macroblocks are

required in QCIF mode. With a 27MHz SYSCLK all macrob-

locks will be coded in less than a 30Hz frame rate period, and

there will be a period of inactivity before FRMIN goes active

again. During this period the output bus will remain static at all

ones, and no output strobe ( DCLK ) will be produced.

PCLK

YUV7:0

10ns

20ns

0ns

SCLK/2

20ns

N.B. All timings given are MINIMUM values.

Fig 6 : Timing at YUV Port

5

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