VP2611 Просмотр технического описания (PDF) - Mitel Networks

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VP2611

H.261 Encoder

Mitel Networks 

VP2611

Frame Store Manager

The previous picture is stored in an external CIF DRAM

frame store, which is connected by a glueless interface. The

internal Frame Store Manager controls all read, write, and

refresh operations to these DRAMs. No provision is made to

allow the use of smaller DRAM's, if only QCIF operation is

required.

During the coding of each macroblock columns of the

search window are read from these DRAMs, and finally the

"best fit" macroBlock is obtained. At the completion of coding

the fully processed new macroblock is written to the DRAM's,

after it has been decoded again. In this way the frame store

maintains a bit-accurate duplicate of the image seen by the

Decoder (excepting transmission errors).

Several configurations are possible to make the required

128Kx16 store. Two 64K x 16 DRAMs could be employed; in

this case use the default 1M DRAM mode when setting up the

chip. Otherwise, a single 256K x 16 DRAM or four 256K x 4

DRAMs could be used. In these last two cases use OE1 as

ADR8, RW1 as R/W, and do not connect RW2 and OE2. Also,

use the Setup instruction at the CPORT to put the device into

4M DRAM mode.

Table 1 details the critical timing parameters which the

external DRAM must meet with SYSCLK running at 27MHz.

Note that, if used at slower speeds, the requirements on the

DRAM timing are relaxed with the exception of refresh. The

number of refresh cycles the VP2611 produces is directly

proportional to the SYSCLK frequency.

Discrete Cosine Transform

This circuit performs a Discrete Cosine Transform on each

8x8 sub block, whether in inter or intra mode. In intra mode,

eight bit pixel data is used, with a ninth implied sign bit ( all pixel

data is positive ). In inter mode the difference between the

current and best fit previous block is used. This will be a two's

complement number. Twelve bit coefficients are produced by

the DCT, and passed on to the quantizer.

Quantize

This section quantizes the results of the DCT by dividing

the 12 bit output from the DCT with a host supplied value. The

5 bit quantization value supplied corresponds to division of the

12 bit coefficients ( range ± 2048 ) by values from 2 to 62, but

in steps of 2. This variable quantization strategy allows the

volume of data generated by the encoder to be adjusted

dynamically, depending on the fullness of the transmission

buffer. For H.261 applications it uses the quantisation value

provided at the control port during the previous Macroblock

period (or at some earlier time). An option is provided which

allows two quantisation values to be used, one for use with

inter coded macroblocks, and the other for use with intra

coded macroblocks.

As specified in H.261, the DC coefficient of an Intra coded

Block is treated differently and the 12 bit value is always

divided by 8.

When the quantization value is small, and the DCT coef-

ficient is large, there is a danger of overflow in the eight bit

output. To avoid this a clipping circuit is included at the output

of the quantizer, which saturates at the maximum values.

4

Zig Zag Scan

This is essentially an address generator which reorders

the DCT coefficients according to the standard zig-zag scan

pattern. This has the effect of concentrating the significant

coefficients at the beginning of the sub-block, improving the

efficiency of the Run Length Coder.

Run Length Coder

Each coefficient output from the zig zag scan is examined.

If it is non-zero, then the Run Length Coding circuit will pass

the coefficient magnitude to the output port along with its zero

count i.e. the number of zero magnitude coefficients preced-

ing it within the same 8x8 sub-block.

Inverse Quantize

This circuit replicates the operation of the inverse quan-

tizer in the decoder. It reconstructs the 12 bit DCT coefficients

from the 8 bit quantized inputs, using the 5 bit quantization

value. This is achieved using the following formulae.

If QUANT is odd :

REC = QUANT*(2*LEVEL+1) : LEVEL > 0

REC = QUANT*(2*LEVEL-1) : LEVEL < 0

If QUANT is even :

REC = QUANT*(2*LEVEL+1)-1 : LEVEL > 0

REC = QUANT*(2*LEVEL-1)+1 : LEVEL < 0

For Intra Coded DC Coefficients :

REC = 8*LEVEL

except if LEVEL=255 when REC=1024

If LEVEL=0 then REC=0 in all cases.

The reconstructed values (REC) are passed through a

Clipping Circuit in case of arithmetic overflow.

Thus, the Inverse Quantizer restores the DCT coefficients

to their original value but with quantisation error.

Inverse DCT

This circuit replicates the operation of the Inverse Cosine

Transform in the Decoder, and outputs 9 bit signed pixel data

(intra mode) or pixel difference data (inter mode). The IDCT

fully meets the CCITT specification.

Reconstruction Adder

In Inter Mode, the IDCT data is added to the best fit block

from the previous frame store. In Intra mode, the IDCT data is

simply added to zero. After the adder, the sign bit is removed

from the result to give 8 bit pixels. Clipping circuits ensure that

any pixels with values exceeding 255 are clipped to 255, and

any with negative values are clipped to zero (such values are

possible due to quantization noise).

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