VP2611CGGH1R Просмотр технического описания (PDF) - Mitel Networks

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VP2611CGGH1R

H.261 Encoder

Mitel Networks 

VP2611

PIN DESCRIPTIONS

YUV7:0

This input bus accepts YUV data one pixel at a

time from the preprocessor, clocked in on the

rising edge of PCLK.

PCLK

This signal is used to strobe in data at the YUV

port and must be derived by dividing SYSCLK

with an integer greater than one.

FRMIN

This input should be pulled high to prepare the

VP2611 to code a new frame. It must be held

high for at least one SYSCLK cycle and then

must be pulled low again before the next frame

begins. The VP2611 will respond to the rising

edge of FRMIN by asserting REQYUV

appproximately 184 SYSCLK cycles later.

REQYUV

This output is pulled high to request that YUV

data be input for a new MacroBlock. It is pulled

low again 1871 SYSCLK cycles later. It re-

mains low during Dummy MacroBlocks and

during the lay period between frames.

DBUS7:0

This output bus serves several functions as

defined by DMODE3:0. In addition to providing

the quantized coefficients and motion vectors,

it is used to output control information.

DMODE3:0

Output flag port for DBUS7:0 bus. The value at

this port identifies the data type appearing on

DBUS7:0 during the same period.

DCLK

This output pulses high for a minimum of 37ns

each time new data is output on DBUS or

DMODE. It can be used as an edge sensitive

strobe signal or a level sensitive "valid" signal.

SW15:0

This bidirectional port is connected to the

frame store.

RAS

Row Address Strobe output for the external

DRAMs.

CAS

Column Address Strobe output for the external

DRAMs.

R/W1

R/W2

Read/Write control for external DRAM 1.

Read/Write control for external DRAM 2.

N/C if 256k DRAMs.

OE1

Output Enable control for external DRAM 1

or ADR8.

OE2

ADR7:0

CBUS7:0

Output Enable control for external DRAM 2.

N/C if 256k DRAMs.

Address output for the external DRAMs.

Bi-directional data bus for use by a Microproce-

ssor. Data and insructions are clocked on and

off the chip on the rising edge of CSTR.

CSTR

CEN

CADR

SYSCLK

Data strobe for the CBUS port.

An enabling signal for the CBUS port.

When high, this signal defines CBUS as a data

bus, and when low as an instruction input.

System clock, run at 27MHz maximum. The

clock must be high for between 35% and 65%

of each clock cycle. This clock is used for all

internal operations.

RESET

TCK

TMS

TDI

TDO

Active low power on reset which must be held

low for at least 2064 cycles.

Test clock for JTAG.

Test Mode Select for JTAG.

Input JTAG test data.

Output JTAG test data.

TRST

Reset JTAG controller (active low).

NOTE:

"Barred" active low signals do not appear with a bar in the

main body of the text.

YUV

BLOCK

FORMAT

FORWARD PATH

SUB DCT

Q

INTER/INTRA

DECISION

PROCESSOR

Q Step

Force

Intra

MOTION

VECTOR

ESTIMATOR

Search

Window

LOW

PASS

FILTER

Force

Predicted Filter

block

FRAME STORE INTERFACE

Zig Zag

IQ

IDCT

RLC

Motion Vectors

ADD

Force

Intra

Force

Filter

CONTROL Block Info

LOGIC

DATA

BUS

BUS

FLAGS

ADDRESS

CONTROL

DATA

HOST DATA & CONTROL

Fig 2 : Simplified Block Diagram

2

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