VP2611CGGH1R Просмотр технического описания (PDF) - Mitel Networks
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VP2611CGGH1R Datasheet PDF : 14 Pages
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VP2611
Initialising the VP2611
On power-up, RESET should be low and must remain low
for at least 2064 cycles of SYSCLK. After RESET is pulled
high, FRMIN may be activated to start the first frame. Before
activating FRMIN for the first time, it is advisable to use the
CBUS to implement a FAST UPDATE for the first frame (i.e.
all blocks Intra coded).
JTAG Test Interface
The VP2611 includes a test interface consisting of a
boundary scan loop of test registers placed between the pads
and the core of the chip. The control of this loop is fully JTAG/
IEEE 1149-1 1990 compatible. Please refer to this document
for a full description of the standard.
The interface has five dedicated pins: TMS, TDI, TDO,
TCK and TRST. The TRST pin is an independent reset for the
interface controller and should be pulsed low, soon after
power up; if the JTAG interface is not to be used it can be tied
low permanently. The TDI pin is the input for shifting in serial
instruction and test data; TDO the output for test data. The
TCK pin is the independent clock for the test interface and
registers, and TMS the mode select signal.
TDI and TMS are clocked in on the rising edge of TCK, and
all output transitions on TDO happen on its falling edge.
Instructions are clocked into the 8 bit instruction register
(no parity bit) and the following are available.
Instruction Register Name
( MSB first )
11111111
00000000
01000000
XX001011
BYPASS
EXTEST (No inversion)
INTEST
SAMPLE/PRELOAD
Timing details for the JTAG control signals are shown in fig
11.The maximum TCK frequency is 5 MHz.
The test registers, their positions in the boundary loop and
the corresponding i/o pad are detailed in Table 4. Note that the
three state control signals also have test registers associated
with them which are labelled as TRI in Table 4. DHz is an
output enable for all signals to the DRAM. The order given in
Table 4 determines the serial data stream needed for JTAG
testing.
TCK
Signal
TCK
Signal
Tsu
Thd
Tprop
TMS toTCK timing
TDI to TCK timing
Chip i/p to TCK timing
Tsu
Thd Tprop
15
5
15
5
15
5
TCK to TDO timing
20
Fig 11 : JTAG Interface timing
10
Pad
Type Reg No Pad
Type Reg No Pad
Type Reg No
RESET IN
93 DBUS5 OP
62
IN
31
CADR
IN
92 DBUS6 OP
61 SW1
OP
30
CSTR
IN
91 DBUS7 OP
60
IN
29
CEN
IN
90 SW15 OP
59 SW0
OP
28
CBUS0 OP
89
TRI
58
IN
27
TRI 88
IN
57
DHZ
TRI
26
IN
87 SW14 OP
56
RAS
OP
25
CBUS1 OP
86
IN
55
CAS
OP
24
IN
85 SW13 OP
54
RW1
OP
23
CBUS2 OP
84
IN
53
RW2
OP
22
IN
83 SW12 OP
52
OE1
OP
21
CBUS3 OP
82
IN
51
OE2
OP
20
IN
81 SW11 OP
50
ADR0 OP
19
CBUS4 OP
80
IN
49
ADR1 OP
18
IN
79 SW10 OP
48
ADR2 OP
17
CBUS5 OP
78
IN
47
ADR3 OP
16
IN
77 SW9
OP
46
ADR4 OP
15
CBUS6 OP
76
IN
45
ADR5 OP
14
IN
75 SW8
OP
44
ADR6 OP
13
CBUS7 OP
74
IN
43
ADR7 OP
12
IN
73 SW7
OP
42
PCLK IN
11
DCLK
OP
72
IN
41
YUV7 IN
10
DMODE0 OP
71 SW6
OP
40 YUV6 IN
9
DMODE1 OP
70
IN
39 YUV5 IN
8
DMODE2 OP
69 SW5
OP
38
YUV4 IN
7
DMODE3 OP
68
IN
37
YUV3 IN
6
DBUS0 OP
67 SW4
OP
36 YUV2 IN
5
DBUS1 OP 66
IN
35
YUV1 IINN
4
DBUS2 OP
65 SW3
OP
34
YUV0 IN
3
DBUS3 OP
64
IN
33
SYSCLK IN
2
DBUS4 OP
63 SW2
OP
32
FRMIN IN
1
REQYUV OP
0
Table 4 Pin and JTAG test registers
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