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AN6846 Просмотр технического описания (PDF) - Fairchild Semiconductor

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AN6846 Datasheet PDF : 8 Pages
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AN-6846
APPLICATION NOTE
Figure 13.Universal Line Voltage Compensation for
Constant Output Power Limit
Two-level Over-Current Protection (OCP)
The cycle-by-cycle current limiting shuts down the PWM
immediately when the switching current is over the peak-
current threshold. In addition, an over-current protection
circuit is built-in. When the switching current is higher than
the OCP threshold, the internal counter starts counting up.
When the switching current is lower than the OCP threshold,
the internal counter counts down. When the total
accumulated counting time is more than OCP delay time
(SG6846A: 1600ms; SG6846C: 110ms), the controller is
latched off.
By adjusting the RS resistance to let the peak-current at
maximum load under OCP threshold and over this threshold
at peak load condition, the two-level OCP protection is
enabled. These functions are especially designed for an
SMPS with surge current output, such as for printers,
scanners, and motor drivers.
Thermal Protection
A constant current, IRT, is provided from the pin RT.
The resistor connected to pin RI determines its magnitude:
IRT = 1.8V / RI
(8)
For example, IRT = 70µA if RI = 26KΩ.
For over-temperature protection (OTP), an NTC thermistor
RT in series with a resistor Ra can be connected between the
RT pin and ground. When the voltage of the RT pin drops
below 1.065V, PWM output is latched off. A debounce time
around 100µs is added to prevent false triggering. After the
latch is reset and cleared (SG6846CX: VRT>1.165V;
SG6846LX: AC unplugged), PWM turns on again. If the RT
pin is not used, connect a 100kΩ resistor between the RT
pin and ground to disable this thermal protection function.
Beside NTC and Ra, a capacitor should be connected to RT
pin to eliminate switching noise. This capacitor’s value is
less than 1nF (shown as Figure 14).
Figure 15.T C1 (<1nF) Connect to RT Pin
Figure 14.Timing Chart for Two-level Over-Current
Protection (OCP)
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents the controller from
over-voltage destruction. The VDD voltage rises when an
open-loop failure occurs. Once the VDD voltage exceeds
23.6V for around 100µs, the power supply latches off.
Lab Note
Before rework or solder/desolder on the power supply,
discharge the primary capacitors by an external bleeding
resistor. Otherwise, the PWM IC may be destroyed by
external high voltage during solder/desolder.
This device is sensitive to ESD discharge. To improve
production yield, the production line should be ESD
protected according to ANSI ESD S1.1, ESD S1.4, ESD
S7.1, ESD STM 12.1, and EOS/ESD S6.1.
© 2008 Fairchild Semiconductor Corporation
Rev. 1.3.2 • 9/26/08
6
www.fairchildsemi.com

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